Testing apparatus for semiconductor memory device

Details Testing apparatus for semiconductor memory device Testing apparatus for semiconductor memory device

1999-12-16

2003-03-18

Baderman, Scott (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S042000, C714S711000, C714S718000

Reexamination Certificate

active

06535993

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor testing apparatus, and particularly a semiconductor testing apparatus for specifying a position of a faulty memory cell in a semiconductor memory device and determining whether it can be repaired by a redundant circuit or not.
2. Description of the Background Art
In view of product yield and others, a semiconductor memory device is generally provided internally with a redundant circuit so that a faulty portion (faulty memory cell) can be repaired by the redundant circuit. The redundant circuit, which will be referred to as a “spare circuit” hereinafter, is formed of a spare row (X) and a spare column (Y). A row or column in which a faulty memory cell (faulty bit) is present is replaced with the spare row or the spare column so that the faulty bit is repaired.
For repairing a faulty bit, a test is conventionally performed on a semiconductor memory device referred to as a “semiconductor memory” hereinafter, after wafer process of the semiconductor memory is completed. In this test, it is determined whether a faulty bit is present in the semiconductor memory or not. When a faulty bit is detected, it is determined whether the faulty bit can be repaired by the spare circuit or not.
FIG. 21
schematically shows a structure of a conventional semiconductor testing apparatus, which will be referred to as a “tester” hereinafter. In
FIG. 21
, a tester
102
includes a pattern generator
103
for generating a test pattern for a semiconductor memory under test
1
, in accordance with a predetermined sequence to write the test pattern into semiconductor memory under test
1
, a pass/fail determinator
104
for comparing data read from semiconductor memory under test
1
with an expected value to determine pass/fail of a read bit (memory cell), and a repairability determining device
105
for determining whether semiconductor memory under test
1
can be repaired or not, to detect a faulty address in accordance with the result of determination by pass/fail determinator
104
.
FIG. 22
schematically shows a structure of repairability determining device
105
shown in FIG.
21
. Semiconductor memory
1
includes a memory array
1
a
having memory cells arranged in rows and columns.
FIG. 22
shows memory cell array
1
a
having the memory cells arranged in four rows and four columns.
Repairability determining device
105
includes a faulty bit storage memory
106
for storing a position of a faulty bit in memory array
1
a
of semiconductor memory
1
, a row-side faulty bit counter
107
which includes count circuits arranged corresponding to respective rows of faulty bit storage memory
106
, for counting the numbers of faulty bit(s) in the respective rows of faulty bit storage memory
106
, and a column-side faulty bit counter
108
which includes count circuits arranged corresponding to the respective columns of faulty bit storage memory
106
for counting the numbers of faulty bit(s) in the respective columns.
Faulty bit storage memory
106
has storage capacity similar to that of memory array
1
a
of semiconductor memory
1
, and can store information indicating a faulty bit, in the position determined as the faulty bit in accordance with the pass/fail determination result applied from pass/fail determinator
104
. Operation of tester
102
and repairability determining device
105
shown in
FIGS. 21 and 22
. will now be described with reference to a flow chart of FIG.
23
.
First, a test operation is effected on semiconductor memory under test
1
(step S
1
). In this test operation, pattern generator
103
first generates a predetermined test pattern in accordance with a predetermined sequence, and tester
102
writes the test pattern generated by pattern generator
103
into semiconductor memory under test
1
(step S
1
a
).
Then, test pattern data is written into all the bits of semiconductor memory under test
1
, and then the data is read from semiconductor memory under test
1
. The data read from semiconductor memory under test
1
is applied to pass/fail determinator
104
. Pass/fail determinator
104
is already supplied with expected values of the read data in accordance with the test pattern generated from pattern generator
103
. Pass/fail determinator
104
makes a comparison between an expected value of data read from semiconductor memory under test
1
and a bit value of the data read from semiconductor memory
1
, and determines whether the memory cell from which the data is read is a faulty bit or not in accordance with the result of comparison (step S
1
b
).
When a faulty bit is present, pass/fail determinator
104
sends the faulty bit information to repairability determining device
105
. Repairability determining device
105
stores the information indicating the fault at the position in faulty bit storage memory
106
corresponding to the position of the faulty bit in memory array
1
a,
in accordance with the faulty bit information sent from pass/fail determinator
104
. Each of row-side and column-side faulty bit counters
107
and
108
increments the number of faulty bits on a corresponding row or column by one when faulty bit information is written into faulty bit storage memory
106
(step S
2
). This determining operation is repeated for all the bits of memory array
1
a
of the semiconductor memory under test (step S
3
).
In the flow chart of
FIG. 23
, it is shown that the testing process returns to step S
1
a
of applying a new test pattern before the determination of all the bits is completed. This represents such a sequence that fault detection of all the bits is performed with a test pattern, and then another test pattern is applied to semiconductor memory under test
1
for performing detection of faulty bits in a similar manner. As the test patterns, there are various patterns such as a test pattern for detecting inter-bit interference and a test pattern formed of the same data for detecting the fault of a memory cell itself. These various test patterns are applied for detecting the faulty bit.
When the determination of all the bits of memory array
1
a
with all the test patterns is completed, repairability determining device
105
then determines the repairability (step S
4
). As shown in
FIG. 22
, it is now assumed that faulty bits are present at the 3rd column in the 1st and 2nd rows of memory array
1
a
when the determination of all the bits is completed. In this state, the count of each of the count circuits in the 1st and 2nd rows of row-side faulty bit counter
107
goes to 1 corresponding to the faulty bit and, in column-side faulty bit counter
108
, the count of the count circuit corresponding to the 3rd column goes to 2. Based on the above distribution of faulty bits, it is determined whether the faulty bits can be repaired or not in accordance with a predetermined algorithm (not shown).
When it is determined that the repair is possible, programming of a faulty address is performed by fuse blow in the wafer process, and the faulty bit(s) are repaired by replacement with the spare row circuit(s) and/or spare column circuit(s).
For example, in the structure shown in
FIG. 22
, the 3rd column of memory array
1
a
is replaced with the spare column.
Faulty bit storage memory
106
has a storage capacity equal to or larger than the storage capacity of semiconductor memory under test
1
for storing the faulty bit positions of semiconductor memory under test
1
. Repairability determining circuit
105
refers to faulty bit storage memory
106
for determining the repairability of a faulty bit. With increase in storage capacity of the semiconductor memory under test, therefore, the storage capacity of faulty bit storage memory
106
included in repairability determining circuit
105
must be increased, and the scale of repairability determining circuit
105
is increased. For increasing the storage capacity of the faulty bit storage memory, the memory must be extended, and the peripheral circuit structure must be changed for supporting the

Affiliated with

Also associated with

Rating

Testing apparatus for semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Testing apparatus for semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Testing apparatus for semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3051574