Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2006-09-01
2008-10-21
Chung, Phung M (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S736000, C714S738000
Reexamination Certificate
active
07441166
ABSTRACT:
There is provided a testing apparatus including: a pattern generator that generates an address signal and a data signal to be supplied to a plurality of memories under test and an expectation signal; a plurality of logic comparators that generate fail data when an output signal output from the plurality of memories under test and the expectation signal are not identical with each other; a plurality of fail memories that store the fail data generated from the plurality of logic comparators; a plurality of memory controllers that generate bad address information showing a bad address in the memory under test based on the fail data stored on the plurality of fail memories; a plurality of universal buffer memories that store the bad address information generated from the plurality of memory controllers; and a plurality of bad information writing sections that concurrently write bad information into the bad address in the plurality of memories under test, which is shown by the bad address information stored on the plurality of universal buffer memories.
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International Search Report issued in International Application No. PCT/JP2005/005171 mailed on Jun. 28, 2005 and English translation thereof, 4 pages.
Ohsawa Toshimi
Sato Kazuhiko
Yamada Masuhiro
Advantest Corporation
Chung Phung M
Osha & Liang LLP
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