Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed
Reexamination Certificate
2003-09-29
2004-11-09
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
With measuring or testing
Electrical characteristic sensed
C438S005000, C438S010000, C438S014000
Reexamination Certificate
active
06815237
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor processing, and more particularly to on-chip test structures for monitoring etch bias.
2. Description of the Related Art
Of particular interest to semiconductor design and manufacturing is the accurate determination of etch bias (the geometrical difference between the desired or drawn dimensions and the actual produced dimension). Accurate monitoring and control of etch biases is important for device modeling. Etch bias is affected by a number of variables in semiconductor processing, including types of materials doped, dopant types, electrical conductivity or insulation of layers beneath the etched layer, the amount and type of metal exposed during etching, and other variable properties which make anticipating and designing for etch-bias difficult.
Previous methods of monitoring etch bias in semiconductor processing include physically measuring the etch bias using some form of Transmission Electron Microscopy (TEM) or Scanning Electron Microsopy (SEM). For example, H. Leung describes an SEM technique in U.S. Pat. No. 4,717.445 that uses an etch-resistant structure as a reference, against which to optically measure the etch bias in a non-etch-resistant structure. Unfortunately, both TEM and SEM techniques involve stopping to clean the wafer or device of interest, cleaving the structure, and then optically verifying the etch bias. They are destructive to the structure, are time consuming to perform, and may result, in the case of SEM, in needless electron bombardment and further destruction of the sample. In addition to the destructive nature of these two techniques, the industry trend towards structure geometries below one micron precludes their use. Etch bias on the order of 0.1-0.2 microns (sub-micron) is difficult to measure accurately with TEM and SEM techniques.
More recently, etch bias has been determined through a technique called Resistive Line Width Bias (RLWB). This technique calculates the difference between measured and calculated resistance for a particular sample structure. RLWB is effective to measure lateral structures with the goal of finding a cross-sectional area. Unfortunately, RLWB does not work well when the purpose is to find the width of a material junction that has varied doping in a semiconductor device such as at a PN junction or at a junction that has lightly doped and heavily doped sides.
Therefore, there is a need for a technique to measure and monitor etch bias at material junctions that have varied doping for measurements in the sub-micron range.
SUMMARY OF INVENTION
A testing apparatus for determining the etch bias associated with a semiconductor-processing step includes a substrate, a first cathode finger with a first width on the substrate, a second cathode finger with a second width on the substrate, and a cathode platform on the substrate wherein the cathode platform has a third width W″ and a length L″ that are both substantially larger than either of the first and second widths.
In one embodiment of the invention, a method is described to calculate the etch bias, including measuring a capacitance between cathode and anode platforms to calculate a unit area capacitance, measuring a first finger capacitance between a first cathode finger and first anode finger both having a first width and measuring a second finger capacitance between a second cathode finger and second anode finger both having a second width different than the first width. The etch etch bias &Dgr; is calculated from the unit area capacitance, the first finger capacitance and width, and the second finger capacitance and width.
In another embodiment, current measurements are used to calculate etch bias, including measuring a current response to a voltage applied across cathode and anode platforms to calculate a unit area current measuring a current response to a voltage applied across a first cathode finger and first anode finger both having a first width and measuring a current response to a voltage applied across a second cathode finger and second anode finger both having a second width different than the first width. The etch bias &Dgr; is calculated from the unit area current, the first finger current response and width and the second finger current response and width.
REFERENCES:
patent: 4717445 (1988-01-01), Leung
patent: 5386172 (1995-01-01), Komatsu
patent: 5837995 (1998-11-01), Chow et al.
patent: 6697697 (2004-02-01), Conchieri et al.
patent: 2003/0103320 (2003-06-01), Shimada et al.
patent: 2003/0229410 (2003-12-01), Smith et al.
patent: 2004/0047112 (2004-03-01), Yoshida et al.
E. G. Colgan, R.J. Polastre, M. Takeichi and R.L. Wisnieff,Thin-Film-Transistor Process-Characterization Test Structures, Feb. 12, 1998, http://www.research.ibm.com/journal/rd/423/polastre.txt.
Brar Berinder P. S.
Li James Chingwei
Pierson, Jr. Richard L.
Koppel, Jacobs Patrick & Heybl
Rockwell Scientific Licensing LLC
Smith Matthew
Yevsikov Victor V
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