Testing and repair of embedded memory

Details Testing and repair of embedded memory Testing and repair of embedded memory

1996-04-02

1998-11-24

Beausoliel, Jr., Robert W.

Excavating

39518307, G06F 1100

Patent

active

058417842

ABSTRACT:
A method and circuits for coupling a memory embedded in an integrated circuit to interconnect pads during a memory test mode is disclosed. The integrated circuit contains a processor, an embedded memory and a switching circuit for: (1) temporary coupling the memory array and memory peripheral circuits, coupled to the processor during normal operation mode of the circuit, to the interconnect pads of the memory during a memory test mode; (2) and decoupling the interconnect pads from the memory array and peripheral circuits, after the memory is tested, and coupling the memory array and peripheral circuits to the processor.

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patent: 5485424 (1996-01-01), Kawamura

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