Testing and alert device and method for power leakages

Details Testing and alert device and method for power leakages Testing and alert device and method for power leakages

2008-09-11

2011-12-06

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Digital data processing system initialization or configuration

Loading initialization program

C713S001000

Reexamination Certificate

active

08074064

ABSTRACT:
A testing and alert device for power leakages of a computer includes a basic input/output system (BIOS) chip located on a motherboard of the computer, a south bridge chip connected to the BIOS chip, and an alarm device controlled by the BIOS chip. The south bridge chip has a first general purpose input/output terminal capable of being coupled to a ground of an exterior power source. The BIOS chip is capable of detecting the input signal of the first general purpose input/output terminal of the south bridge chip and outputting an alarm command to initiate the alarming device when the input signal from the first general purpose input/output terminal is at a high level.

REFERENCES:
patent: 2005/0173538 (2005-08-01), Tsukuda et al.
patent: 2007/0047904 (2007-03-01), Kimura
patent: 2008/0007884 (2008-01-01), Gries et al.
patent: 2008/0229087 (2008-09-01), Li
patent: 2009/0125123 (2009-05-01), Lu
patent: 2009/0177861 (2009-07-01), Mazzola et al.

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