Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1997-09-29
2000-03-07
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
G06F 1100
Patent
active
060354259
ABSTRACT:
In a computer system having a peripheral bus and a peripheral device coupled together, a method for testing data transfer integrity of the peripheral bus includes the step of transferring first data to the peripheral device via the peripheral bus. Another step of the method includes generating a first error signal if the first data was corrupted during the first data transferring step. The method also includes updating a counter in response to generation of the first error signal. The method further includes generating a second error signal if the counter exceeds a predetermined threshold. Moreover, the method includes the steps of transferring the first data in a first manner, and in response to generation of the second error signal, transferring second data to the peripheral device in a second manner that is different than the first manner. The difference between the first manner and the second manner may include a difference in transfer rate and/or a difference in bus width.
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Caldwell Barry E.
McCombs Craig C.
Beausoliel, Jr. Robert W.
Elmore Stephen C.
LSI Logic Corporation
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