Testing a non-volatile memory

Details Testing a non-volatile memory Testing a non-volatile memory

1995-08-24

1997-05-06

Dinh, Son T.

Static information storage and retrieval

Floating gate

Particular connection

36518905, 36518907, 365201, 36523008, G11C 700

Patent

active

056277806

ABSTRACT:
An integrated circuit memory device has: a memory array; a set of data latches for holding data bits to be stored in the memory array; a plurality of data tracks for supplying data bits to the data latches; a set of address latches for holding address bits for addressing the memory array; a test bus; a data bit routing circuit connected to the data latches for selectively routing data bits to either the memory array or the test bus; an address bit routing circuit connected to the address latches for selectively routing address bits to either the array or the test bus; and an output circuit for outputting data bits and address bits on the test bus. In this way, data bits and address bits can be checked for accuracy against the originally supplied data bits and address bits. Thus, a test can be conducted without requiring data actually to be written to memory cells of the memory.

REFERENCES:
patent: 3710350 (1973-01-01), Yoshitake et al.
patent: 3961252 (1976-06-01), Eichelberger
patent: 3961254 (1976-06-01), Cavaliere et al.
patent: 5175840 (1992-12-01), Sawase et al.
patent: 5287326 (1994-02-01), Hirata
Standard Search Report dated Oct. 24, 1994.

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