Tester of semiconductor memory device and test method thereof

Details Tester of semiconductor memory device and test method thereof Tester of semiconductor memory device and test method thereof

2000-02-24

2003-09-23

Dildine, R. Stephen (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S710000, C714S711000, C714S723000

Reexamination Certificate

active

06625766

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a tester of a semiconductor memory device and a test method thereof, and more particularly to a tester of a semiconductor memory device and a test method thereof, in case of testing the semiconductor memory device having memory cells whose memory capacity does not increase by 2
n
, by which a user can perform a test without changing a test program of the tester.
A conventional tester of a semiconductor memory device (hereinafter referred to as semiconductor memory device) generates addresses to test the semiconductor memory device whose capacity regularly increases by 2
n
. In case that the tester performs a test to the semiconductor memory device whose capacity does not regularly increase by 2
n
, in other words, if the capacity of the memory cells is 2
n
+&agr;, which is in the range of 2
n
to 2
n+1
, a counter which generates read, write and refresh addresses can not count up to 2
n
+&agr;. Only if the counter counts up to 2
n+1
can all the memory cells of the semiconductor memory device be tested. This is because only a single, “prime” bit within a field of bits of a maximum address value is detected, which prime bit represents an address of a 2
n
magnitude, where n is an integer.
In order to test the semiconductor memory device whose capacity does not increase by 2
n
, the user of the tester should make a new test program, which takes a great deal of time and effort. However, the reliability of the semiconductor memory device to be tested by the new test program may not be so satisfactory.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a test method of a semiconductor memory device for precisely generating a desired magnitude of addresses without making a new test program in case the capacity of future semiconductor memory devices does not regularly increase by 2
n
.
It is another object of the present invention to provide a tester of the semiconductor memory device to accomplish the aforementioned object.
In order to accomplish the aforementioned object of the present invention, there is provided a test method of a tester of a semiconductor memory device which records a test pattern into the semiconductor memory device, reads the recorded test pattern to compare with a desired value pattern, detects information on a defect of the semiconductor memory device resulting from the comparison and interprets the information on the defect of the semiconductor memory device, the method comprising the steps of:
setting up minimum and maximum values relevant to a desired capacity of the semiconductor memory device to be tested;
counting up from the preset minimum value;
generating a carry signal, by comparing the preset maximum value with the counted value when the count gets to the preset maximum value. Preferably, the method further comprises thereafter resetting a value to be counted if the carry signal is generated, to thereby generate further test addresses of the semiconductor memory device.
In order to accomplish another object of the present invention, there is provided a tester of the semiconductor memory device which records a test pattern into the semiconductor memory device, reads the recorded test pattern to compare with a desired value pattern, detects information on a defect of the semiconductor memory device resulting from the comparison and interprets the information on the defect of the semiconductor memory device, the tester comprising:
minimum and maximum address registering means for saving minimum and maximum address values relevant to a desired capacity of the semiconductor memory device to be tested;
address counting means for increasingly counting from the minimum value to generate addresses; and
carry signal generating means for generating carry signals, if addresses output from the address counting means and a signal output from the maximum address registering means are the same, to thereby reset the address counting means.


REFERENCES:
patent: 4061908 (1977-12-01), De Jonge et al.
patent: 4669082 (1987-05-01), Tilghman et al.
patent: 4896133 (1990-01-01), Methvin et al.
patent: 5325367 (1994-06-01), Dekker et al.
patent: 5630160 (1997-05-01), Simpson et al.
patent: 5739745 (1998-04-01), Simpson
patent: 6137188 (2000-10-01), Mitchell et al.
patent: 6351833 (2002-02-01), Nomura

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