Testable low inductance integrated circuit package

Details Testable low inductance integrated circuit package Testable low inductance integrated circuit package

1997-10-30

2000-03-07

Clark, Sheila V.

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

257 48, 257692, H01L 2304

Patent

active

060344261

ABSTRACT:
A low inductance integrated circuit package such as a ball grid array having mounting conductors formed on a first side thereof and a die attachment region formed on second side thereof. A plurality of conductors internal to the package interconnect the mounting conductors to the die attachment region. A plurality of diagnostic contact pads are connected to the conductors and configured for ready access by a test probe. The contact pads are preferably provided at a periphery of the package.

REFERENCES:
patent: 5334857 (1994-08-01), Mennitt et al.
patent: 5378981 (1995-01-01), Higgins, III
patent: 5431332 (1995-07-01), Kirby et al.
patent: 5468999 (1995-11-01), Lin et al.
patent: 5640047 (1997-06-01), Nakashima
patent: 5640048 (1997-06-01), Selna

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