Static information storage and retrieval – Read/write circuit – Testing
Patent
1995-03-22
1997-09-16
Nguyen, Viet Q.
Static information storage and retrieval
Read/write circuit
Testing
36518907, 371 211, 371 212, G11C 700
Patent
active
056687648
ABSTRACT:
In order to minimize the time consuming testing of large (e.g., 4 mega-bit) memory units, the units can be designed with alternate test mechanisms incorporated therein. The design for testability (DFT) techniques used in dynamic random access memories to reduce the time required testing use parallel read/write procedures and similar techniques. The technique of the present invention compares actual data signal output with an expected data signal in parallel resulting in a faster determination of the memory status. The additional apparatus is incorporated in the memory unit in the vicinity of the group of storage cells under test. By appropriate selection of the location and function of the apparatus, the test apparatus can result in a smaller chip size, faster processing operation, and lower power consumption. The DFT technique reduces the time for testing by incorporating parallel read/write procedures along with additional test procedures. Little additional apparatus is required for the implementation of the improved test procedures. The benefit derived from the improved testing techniques exceeds the relatively modest implementation cost.
Brady III W. James
Donaldson Richard L.
Holloway William W.
Nguyen Viet Q.
Texas Instruments Incorporated
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