Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle – Yield
Reexamination Certificate
2011-08-30
2011-08-30
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Design of semiconductor mask or reticle
Yield
Reexamination Certificate
active
08010916
ABSTRACT:
Disclosed is a method that predicts test yield for a semiconductor product, prior to design layout. This is accomplished by applying a critical area analysis to individual library elements that are used to form a specific product and by estimating the test yield impact of combining these library elements. For example, the method considers the test yield impact of sensitivity to library element to library element shorts and the test yield impact of sensitivity to wiring faults. The disclosed method further allows die size growth to be traded off against the use of library elements with higher test yield in order to provide an optimal design solution. Thus, the method may be used to modify library element selection so as to optimize test yield. Lastly, the method further repeats itself at key design checkpoints to revalidate initial test yield (and cost) assumptions made when the product was quoted to a customer. Thus, the method provides increased accuracy of test yield estimate from initial sizing through design and further allows designs to be modified to improve test yield.
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Bickford Jeanne
Buehler Markus
Hibbeler Jason D.
Koehl Juergen
Gibb I.P. Law Firm LLC
International Business Machines - Corporation
Kotulak, Esq. Richard M.
Siek Vuthe
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