Test wafer usage forecast modeling method

Data processing: measuring – calibrating – or testing – Testing system – Of circuit

Reexamination Certificate

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C438S014000

Reexamination Certificate

active

06901342

ABSTRACT:
A method for modeling usage of semiconductor test wafers comprises the steps of: calculating an individual demand for test wafers by each of a plurality of tools, assigning respective ones of the plurality of tools to a plurality of levels based on ability of each tool to use wafers that have been processed by another one of the plurality of tools, assigning wafers made available by one of the plurality of tools to at least two other ones of the plurality of tools in proportion to the individual demands of each of the at least two other tools, and determining a total demand for test wafers, based on the number of wafers assigned to each of the plurality of tools in the lowest one of the plurality of levels.

REFERENCES:
Foster et al., Simulation of Test Wafer Consumption in a Semiconductor Facility, IEEE/SEMI Advanced Semiconductor Manufacturing Conference, p. 298-302, 1998.*
Foster et al., “Simulation of Test Wafer Consumption in a Semiconductor Facility”, 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, pp. 298-302.
Popovich et al., “Implementation of a Test Wafer Inventory Tracking System to Increase Efficiency in Monitor Wafer Usage”, 1997 IEEE/SEMI Advanced Semiconductor Manufacturing conference, pp. 440-443.

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