Test system and testing method using memory tester

Details Test system and testing method using memory tester Test system and testing method using memory tester

2002-05-01

2002-12-10

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Converter calibration or testing

C341S155000, C341S144000, C341S126000, C341S094000, C714S030000, C714S743000, C714S725000, C714S728000, C714S738000, C714S718000, C714S724000, C365S201000

Reexamination Certificate

active

06492923

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory tester for verifying operations of a semiconductor memory by detecting whether or not a predetermined expected value is sent back when a predetermined signal is supplied to the semiconductor memory.
2. Description of the Background Art
A memory tester and a logic tester exemplify a semiconductor integrated circuit testing apparatus for testing a semiconductor integrated circuit such as a memory or a logic LSI (large scale integration). As indicated by their names, a memory tester is an apparatus for testing whether or not a memory operates normally, and a logic tester is an apparatus for testing whether or not a logic LSI operates normally.
On the other hand, semiconductor integrated circuits for image processing and for mobile communications are desired to have the capability of processing both of an analog signal and a digital signal. Thus, an analog/digital mixed LSI (mixed signal LSI) containing an analog signal processing part and a digital signal processing part is employed for such circuits. The mixed signal LSI is generally provided with a digital-to-analog converter for converting a digital signal into an analog signal and an analog-to-digital converter for converting an analog signal into a digital signal.
To test a device having the analog-to-digital (A/D) converting function and digital-to-analog (D/A) converting function such as the mixed signal LSI, an analog signal as well as a digital signal needs to be used. Thus, a mixed signal tester capable of outputting both of digital and analog signals is employed for this purpose.
FIG. 10
illustrates an exemplary structure of such mixed signal tester. A mixed signal tester T
2
comprises: a control unit
10
; a digital-to-analog (D/A) converter
11
for converting a digital signal S
10
output from the control unit
10
into an analog signal S
11
and outputting the signal to the outside; and an analog-to-digital (A/D) converter
12
for converting an analog signal S
14
input from the outside into a digital signal S
15
and outputting the signal to the control unit
10
.
The control unit
10
, which represents a central processing unit (CPU) or a digital signal processor (DSP) to which storing means (e.g., a read-only memory (ROM) and a random access memory (RAM)) is connected, is a functional component operated by predetermined software programs stored in the ROM and RAM. The control unit
10
controls the D/A converter
11
and the A/D converter
12
, while exchanging a digital signal S
12
with the outside via another path different from one leading to the D/A converter
11
.
A device under test (DUT)
200
serving as the mixed signal LSI is connected to the mixed signal tester T
2
through pin electronics PE. The pin electronics PE serve as an interface circuit for transmitting a signal from the mixed signal tester T
2
to each pin of the DUT
200
and an output signal from each pin of the DUT
200
to the mixed signal tester T
2
. The pin electronics PE generally comprise, per pin, a driver DR for controlling a signal from the mixed signal tester T
2
and a comparator CP for detecting whether an output signal from each pin of the DUT
200
has a value greater (or smaller) than a predetermined value.
To operate the driver DR and the comparator CP, a voltage source VS is provided, whose potentials at its both terminals are indicated by first and second reference potentials V
1
and V
2
, respectively.
FIG. 11
illustrates an exemplary structure of the comparator CP. The comparator CP includes a High-side comparator C
1
and a Low-side comparator C
2
. One side input terminals of the High-side comparator C
1
and the Low-side comparator C
2
are both supplied with an output signal S
13
from the DUT
200
. The other input terminal of the High-side comparator C
1
is supplied with the first reference potential V
1
through a High-side pad P
1
, and that of the Low-side comparator C
2
is supplied with the second reference potential V
2
through a Low-side pad P
2
.
Output signals S
12
a
and S
12
b
of the High-side comparator C
1
and the Low-side comparator C
2
are transmitted to the control unit
10
, respectively, as the digital signal S
12
. The control unit
10
judges whether a malfunction occurs in the DUT
200
in accordance with the transmitted result. In the case that the signal S
13
from the DUT
200
is an analog signal and thus no comparison need to be made at the comparator CP, the analog signal is output as the signal S
14
from the pin electronics PE to the A/D converter
12
included in the mixed signal tester T
2
.
The mixed signal tester is capable of processing both digital and analog signals
15
and thus have improved convenience, whereas it is expensive due to the complexity of its device structure and that of information processing performed therein.
On the other hand, a memory tester, which processes a digital signal alone, is inexpensive because of its simple device structure and simple information processing compared to those of the mixed signal tester. However, the memory tester is incapable of processing an analog signal, and thus, incapable of testing a device having the A/D converting function and D/A converting function such as the mixed signal LSI.
FIG. 12
illustrates an exemplary structure of the memory tester. The memory tester T
1
c
comprises: a control unit
1
; an algorithmic pattern generator (ALPG)
2
for generating, on the basis of vector data VD, a test pattern as a digital signal to be supplied to a memory cell in each address in a DUT
300
serving as a memory; and a fail bit analyzer (FBA)
3
for analyzing a failure position in the DUT
300
when a failure is found in an output of the DUT
300
, thereby replacing the failure position with a redundant circuit included in the DUT
300
.
The control unit
1
, which represents a CPU or a DSP to which storing means (e.g., ROM and RAM) is connected, is a functional component operated by predetermined software programs stored in the ROM and RAM. The control unit
1
controls the ALPG
2
and the FBA
3
.
The DUT
300
is connected to the memory tester T
1
c
through the pin electronics PE similar to those illustrated in FIG.
10
. Each of signals from the ALPG
2
(an address signal S
1
a
and a data signal S
1
b
, both of which are 8-bit digital signals, for example) is transmitted to the DUT
300
through the pin electronics PE as a signal S
2
.
FIG. 13
is a flow chart showing an operation of the memory tester T
1
c
. First, a test pattern to be supplied to the DUT
300
is designated as vector data VD and is input to the control unit
1
(step ST
1
). The vector data here represents data for designating what type of data (e.g., “0” or “1”) is to be stored in each of a plurality of memory cells arranged in row and column directions in the DUT
300
.
Concrete examples of the vector data VD are shown in
FIGS. 14 and 15
.
FIG. 14
shows an example of vector data that designates the contents of data for each memory cell by “0” or “1” in binary.
FIG. 15
shows another example of vector data that designates the contents of data for each memory cell by applying a predetermined rule.
The respective vector data shown in
FIGS. 14 and 15
, whose X (row) addresses and Y (column) addresses are designated by, e.g., 8 bits, respectively, have data patterns like a checker flag (in which data is aligned with the contents inverted alternatingly as “0”, “1”, “0”, “1” . . . both in the X and Y directions). The vector data shown in
FIG. 14
has the data contents inverted alternatingly as “0”, “1”, “0”, “1” . . . in the same Y address as the X addresses increase one by one. Invoked in the vector data shown in
FIG. 15
is a program having a pattern name of CHK in which an algorithm for previously generating a pattern like a checker flag (e.g., algorithm for inputting data “
1
” to memory cells having X and Y addresses both in odd coordinates and those having X and Y coordinates both in even coordinates, while inputting data “0” to other memo

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