Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-10-20
2002-06-04
Le, N. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S754090
Reexamination Certificate
active
06400173
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a technology effective for application to a test on a semiconductor integrated circuit device and manufacture thereof, and particularly to a technology effective for application to a test in a wafer stage.
As a system for testing a semiconductor device such as a logic integrated circuit (hereinafter called “logic IC”), there has commonly been known a system wherein test pattern data is generated by a device called “tester” and inputted to the logic IC, and a data signal outputted from the logic IC is compared with an expected value to thereby determine it. There is also known a test technology of a BIST (Built in self test) system in which a pattern generator or generating circuit like a pseudo-random number generating circuit, for generating random test patterns is built in a semiconductor device.
In the test system in which the tester externally inputs the test pattern data to the logic IC to thereby perform testing, a shift scan system has been adopted wherein a pre-designed scan path is provided so that flip-flops provided within a semiconductor integrated circuit device are coupled to one another so as to operate as a shift register, and test data is directly inputted to the back of an IC through the scan path and a test result is outputted, whereby the amount of test patterns is reduced.
The BIST system is a self-test conducting system wherein tester functions comprised of a test pattern generating circuit, a test output compressing circuit, a test result determination circuit, etc. are built in a chip for a semiconductor integrated circuit device, and the semiconductor integrated circuit device itself executes a test and outputs the result of test.
On the other hand, the test on the logic IC referred to above has been carried out in two stages of: a probe test done while a probe is being brought into contact with each of pads for semiconductor chips in a wafer stage and a burn-in test done by inserting an IC into a socket provided on a test board in stage at which each semiconductor chip is enclosed in a package. In the burn-in test, a plurality of ICs can be placed on the test board to simultaneously perform their tests.
Incidentally, as the known example in which this type of test system about the semiconductor integrated circuit device has been described in details, there is known a technology disclosed in “LSI Handbook” issued by Ohm Co., Ltd., and (edited) by Institute of Electronics and Communication Engineers of Corporation, P165, P166, Nov. 30, 1984. Configurations or the like of various scan path systems have been described in the present reference.
SUMMARY OF THE INVENTION
It has however been found out by the present inventors that the above test system for the semiconductor integrated circuit device has the following problems.
Namely, since the shift scan system and the BIST system respectively need to form a circuit (scan path) which constitutes a test function, and a test circuit inside a semiconductor integrated circuit device to be tested, a chip size increases. It is thus difficult to bring the semiconductor integrated circuit device into less size.
Further, IC tests are respectively carried out in wafer and package stages. It is also difficult to simultaneously apply a probe to electrode pads of all the chips on a wafer upon probe-used testing in the wafer stage. Therefore, a system in which each individual semiconductor chips are measured in turn, has been adopted. However, a test time becomes very long due to this system. Further, a problem arises in that since the testing of the semiconductor chips one by one causes a decrease in use efficiency of an expensive tester, cost performance is degraded and TAT (Turn Around Time) is not shortened either. Further, the speeding-up and an increase in the number of pins, which are associated with the scale down of the semiconductor integrated circuit device, has been advanced rapidly. Thus, since the usability of the expensive tester is abruptly reduced, a difficulty in investment in the tester further increases.
An object of the present invention is to provide a test technology capable of testing semiconductor chips in a short period of time without using an expensive tester.
Another object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit device, which is capable of testing the semiconductor integrated circuit device without using an expensive tester, thereby making it possible to reduce the total cost necessary for testing.
A further object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit device, which is capable of performing a high-accuracy test upon testing in a wafer stage, thereby shortening a timing interval required between the commencement of design of the semiconductor integrated circuit device and the completion thereof.
A still further object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit device, which is capable of efficiently performing a test while controlling an increase in overhead of a test circuit used for semiconductor chips.
A still further object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit device, which is capable of testing semiconductor chips without using an expensive tester and does not interfere with the post-manufacture semiconductor integrated circuit device.
The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
A summary of typical ones of the inventions disclosed in the present application will be described in brief as follows:
Namely, a test system of the present invention comprises a probe card provided with conductive needles formed in alignment with the placement of electrode pads in semiconductor chips formed on a wafer, a test circuit which is placed on the probe card and conducts tests on the semiconductor chips, based on a test program, and a control device which rewrites a test program in the test circuit and stores therein a test result outputted from the test circuit.
Further, a method of manufacturing a semiconductor integrated circuit device, according to the present invention comprises the following steps of forming a plurality of semiconductor chips each having a desired function on a semiconductor wafer, placing a test circuit connected to needles and operated in accordance with a program to test each semiconductor chip, on a probe substrate having a size corresponding to the semiconductor wafer and having the conductive needles formed thereon in alignment with the placement of electrode pads on the semiconductor chips, superimposing the probe substrate on the semiconductor wafer in such a manner that the needles are brought into contact with the corresponding electrode pads of the semiconductor chips, testing each semiconductor chip by the test circuit, and selecting a semiconductor chip judged to be non-defective, as a product.
According to the above means, since each semiconductor chip on the wafer can be tested by the test circuit placed on the probe substrate, testing can be done without using an expensive tester, thereby making it possible to reduce the total cost necessary for testing. Further, since a high-accuracy test can be carried out upon testing in a wafer stage, it is not necessary to make a test again after packaging. Alternatively, a post-packaging test can be simplified. Thus, a time interval required between the commencement of design of a semiconductor integrated circuit device and the completion thereof can be shortened.
Preferably, programmable logic ICs (FPGA) capable of configuring arbitrary logic are provided on the probe substrate in association with the respective semiconductor chips, and the test circuit is configured within each programmable logic IC based on the design data described in hardware description language, and each semiconductor chip is test
Fukiage Hiroshi
Sato Masayuki
Shimizu Isao
Hitachi , Ltd.
Kerveros James
Le N.
Mattingly Stanger & Malur, P.C.
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