Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Patent
1999-02-18
2000-06-06
Thomas, Tom
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
257797, H01L 2358, H01L 23544
Patent
active
060721928
ABSTRACT:
The present invention advantageously provides a method for determining lithographic misalignment of a via relative to an electrically active area. An electrically measured test structure is provided which is designed to have targeted via areas shifted from the midline(s) of a targeted active area(s). Further, the test structure is designed to have a test pad(s) that electrically communicates with the targeted active area(s). Design specifications of the test structure require the targeted via areas to be offset from the midline(s) of the active area(s) by varying distances. The above-mentioned method involves processing the designed test structure. An electrical signal may then be applied to conductors coupled to each of the vias while it is also being applied to the test pad. The resulting electrical response should be proportional to the distance that a via is misaligned from its desired location. Using the electrical responses for all the vias, it is possible to determine the direction and amount of misalignment.
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Fulford Jr. H. Jim
Gardner Mark I.
Hause Fred N.
Advanced Micro Devices , Inc.
Daffer Kevin L.
Thomas Tom
Vu Hung Kim
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