Test structure responsive to electrical signals for determining

Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure

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H01L 2358

Patent

active

061181374

ABSTRACT:
The present invention advantageously provides a method for determining lithographic misalignment of a conductive element relative to a via. An electrically measured test structure is provided which is designed to have targeted via areas shifted from midlines of corresponding targeted conductor areas. Further, the test structure is designed to have a test pad that electrically communicates with the targeted via areas. Design specifications of the test structure require the midlines of the conductor areas to be offset from the via areas by varying distances. The above-mentioned method involves processing the designed test structure. An electrical signal may then be applied to each of the conductors while it is also being applied to the test pad. The resulting electrical response should be proportional to the distance that a conductor is misaligned from its desired location. Using the electrical responses for all the conductors, it is possible to determine the direction and amount of misalignment.

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