Test structure formation in semiconductor processing

Details Test structure formation in semiconductor processing Test structure formation in semiconductor processing

2011-04-26

2011-04-26

Pert, Evan (Department: 2893)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Having substrate registration feature

C438S014000, C257S048000, C257SE23179

Reexamination Certificate

active

07932157

ABSTRACT:
Test structures are formed during semiconductor processing. The test structures allow performance characteristics to be monitored as the process proceeds. The test structures are formed with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent levels are patterned. The manner of using the mask also allows different types of test structures having different features to be formed. The different types of test structures can provide insight into performance characteristics of different types of devices.

REFERENCES:
patent: 5308682 (1994-05-01), Morikawa
patent: 5892291 (1999-04-01), Narimatsu et al.
patent: 5936311 (1999-08-01), Watrobski et al.
patent: 5960296 (1999-09-01), Auzino et al.
patent: 6071656 (2000-06-01), Lin
patent: 6238939 (2001-05-01), Wachs et al.
patent: 6362491 (2002-03-01), Wang et al.
patent: 6589713 (2003-07-01), Okoroanyanwu
patent: 6617669 (2003-09-01), Saito
patent: 6627530 (2003-09-01), Li et al.
patent: 6819426 (2004-11-01), Sezginer et al.
patent: 6949462 (2005-09-01), Yang et al.
patent: 7071565 (2006-07-01), Li et al.
patent: 7234244 (2007-06-01), Lindberg
patent: 7553611 (2009-06-01), Chen et al.
patent: 2004/0207097 (2004-10-01), Carpi et al.
patent: 2004/0259322 (2004-12-01), Lu et al.
patent: 2006/0222962 (2006-10-01), Chen et al.
patent: 2229419 (1990-09-01), None
patent: 10-1998-0016943 (1998-06-01), None
patent: WO 2006/105326 (2006-10-01), None
Non Final Office Action for U.S. Appl. No. 11/772,130, dated Mar. 24, 2009.
Notice of Allowance for U.S. Appl. No. 11/772,130 dated Jan. 11, 2010.
Final Office Action for U.S. Appl. No. 11/772,130 dated Oct. 20, 2009.
Non-Final Office Action for U.S. Appl. No. 11/772,137 dated Mar. 1, 2010.
Notice of Allowance cited in U.S. Appl. No. 11/772,137 dated Jul. 19, 2010.
Restriction/Election cited in related U.S. Appl. No. 11/772,130 dated Nov. 28, 2008.
Notice of Allowance cited in related U.S. Appl. No. 11/772,130 dated Sep. 15, 2010.
Supplemental Notice of Allowability cited in U.S. Appl. No. 11/772,137 dated Aug. 5, 2010.
Notice of Allowance cited in U.S. Appl. No. 11/772,130 dated Jun. 28, 2010.
Notice of Allowance cited in U.S. Appl. No. 11/772,137 dated Aug. 19, 2010.
First Office Action in Related Chinese Application No. 200880022858.0 dated Jan. 19, 2011.

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