Test structure for metal CMP process control

Details Test structure for metal CMP process control Test structure for metal CMP process control

2001-02-20

2003-11-25

Nguyen, Tu T. (Department: 2877)

Optics: measuring and testing

Inspection of flaws or impurities

Surface condition

Reexamination Certificate

active

06654108

ABSTRACT:

FIELD OF THE INVENTION
The present invention is in the field of optical monitoring techniques, and relates to a test structure to be formed on a real metal-based patterned structure, and a method of controlling a process of chemical mechanical planarization (CMP) applied to the metal-based patterned structure utilizing the test structure. The invention is particularly useful in the manufacture of semiconductor devices such as wafers.
BACKGROUND OF THE INVENTION
In the manufacture of semiconductor devices, aluminum has been used almost exclusively as the main material for interconnects. However, recent developments in this field of the art have shown that copper is poised to take over as the main on-chip conductor for all types of integrated circuits. Compared to aluminum, copper has a lower resistance, namely, less than 2 &mgr;&OHgr;-cm, even when deposited in narrow trenches, versus more than 3 &mgr;&OHgr;-cm for aluminum alloys. This property is critically important in high-performance microprocessors and fast static RAMs, since it enables signals to move faster by reducing the so-called “Resistance-Capacitance”(RC) time delay. Additionally, copper has a superior resistance to electro-migration, which leads to lower manufacturing costs, as compared to aluminum-based structures.
During the manufacture of semiconductor devices, a semiconductor wafer undergoes a sequence of photolithography-etching steps to produce a plurality of patterned layers (stacks). Then, depending on the specific layers' structure or a specific production process, the uppermost layer of the wafer may or may not undergo a CMP process to provide a smooth surface of this layer.
When manufacturing aluminum-based structures, the application of a CMP process to the uppermost layer having aluminum-containing regions is usually not needed. As for the copper-based structures (or tungsten-based structure as well), the manufacturing process requires the CMP to be used for removing the residuals of metal. This is true also for processes where aluminum is deposited by the single or dual Damascene process.
With the conventional technology of planarization, interlayer dielectric—ILD polishing occurs after every metal deposition and etching step. The same is not true for damascene processing, wherein the post-polish surface is expected to be free of topography. However, topography is induced because of erosion of densely packed small feature arrays and dishing of the metal surface in large features.
Copper CMP is more complex because of the following: On the one hand, barrier layers (such as tantalum or tantalum nitride) should be removed completely to prevent the so-called “under-polishing” of the wafer, in which case the wafer's surface contains residuals of a layer to be removed. On the other hand, copper should be removed without an excessive over-polishing of any feature (erosion or dishing). This is difficult to implement, because current copper deposition processes are not as uniform as the oxide deposition process. An additional problem is an accumulated layer-by-layer topography or non-planarity across the wafer's surface caused by erosion and dishing effects.
“Erosion” is the phenomenon while that develops during the copper polishing process.
FIG. 1
illustrates a stack-like copper-based structure
10
after the application of a CMP process thereto. The structure
10
includes an ILD bottom layer
12
, the so-called “etch stop” layer
14
(e.g., SiN), ILD layer portions
16
a
and
16
b,
and a dense structure
20
including spaced-apart regions of a copper layer, generally at
18
, spaced from each other by ILD layer portions
22
(isolated from the surrounding oxide by a thin barrier layer, which is not specifically shown). Hence, the stack layers of the dense structure
20
are composed of the ILD layer portions
22
and the copper layer portions
18
, and are surrounded by the ILD layer portions
16
a
and
16
b.
Such a composite structure
10
having non-uniform mechanical and chemical properties imposes a different a polishing rate or removal distribution over the regions
16
a
,
16
b
and
20
. Due to different chemical and mechanical properties of the ILD layer portions
16
a
-
16
b
, as compared to those of the small features in the dense metal-containing (copper) region
20
, in some cases, the polishing process proceeds quicker above the region
20
than above the portions
16
. The CMP results in a bent-like local profile
24
(concave) of the upper surface of the structure
20
. The existence of the profile
24
is called “erosion”, presenting the direct loss of ILD and metal (e.g., copper) within a region
22
a.
Due to the above-mentioned factors, an additional effect, the so-called “metal line recess” designated
26
takes place presenting another type of defect on the wafer induced by the CMP process applied thereto. Yet another undesirable type of defect induced on the wafer's surface by the CMP process is an effect of barrier layer residues, designated
28
, and an effect of the metal polishing called “dishing” and relating to the non-uniform thickness removal across a relatively large non-patterned metallic area.
One possible solution for minimizing the above-mentioned negative effects consists of a tight control of the CMP process, e.g., using a spectroscopy-based optical system (such as the NovaScan 210 commercially available from Nova Measuring Instruments Ltd., Israel). However, as the measured layer level increases, the complexity of the layer stack (consisting of multiple levels of OX/Etch Stop/OX/Cap layers) impairs the measurement accuracy. This is due to the fact that optical measurements are performed in predetermined sites within the wafer's dies consisting of measuring the optical response of a top layer stack in these sites while the measured parameters are affected by underlying layers. Separating the influence of underlying layers from that of the top layer stack signal presents a sophisticated problem.
SUMMARY OF THE INVENTION
There is accordingly a need in the art to facilitate the control of a CMP process when being applied to a patterned structure such as a semiconductor wafer having metal (e.g., copper) regions, by providing a novel test structure for tight control of the CMP process by processing the test structure with the same CMP as the patterned structure with real features and applying optical measurements to the test structure.
The main idea of the present invention consists of providing such a test structure that, when optical measurements are applied to a measurement area of the top surface of the test structure to detect a light response (in particular, reflection) of the measurement area, the contribution of layers or levels underneath the measurement area to the light response is substantially reduced. Additionally, the test structure is such that, when it is processed by the CMP, a desirable planarity of the measurement area within the test structure is provided. This is implemented by providing the test structure with at least two structures aligned along a vertical axis in a spaced-apart parallel relationship, each pattern structure comprising at least one pattern zone containing spaced-apart metal regions, the test structure thereby comprising at least one pair of vertically aligned upper and lower pattern zones. The upper and lower pattern zones in each pair have different patterns (i.e., different pitch values and, optionally, also different duty cycle values), and are oriented with respect to each other such that the metal regions of the lower pattern are located underneath the spaces between the metal regions of the upper pattern within the measurement area.
Thus, according to one aspect of the present invention, there is provided a test structure, which is to be formed on a patterned structure, progressing on a production line and having a pattern area having metal-containing regions and being representative of real features of the patterned structure, so as to enable concurrent application of a Chemical Mechanical Plana

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