Test structure for improved vertical memory arrays

Details Test structure for improved vertical memory arrays Test structure for improved vertical memory arrays

2005-08-16

2005-08-16

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

C257S301000, C257S302000

Reexamination Certificate

active

06930325

ABSTRACT:
An integrated circuit arrangement that has an integrated test structure is provided. The integrated circuit arrangement includes a transistor array having vertical FET selection transistors electrically coupled to storage capacitors of an assigned memory cell array, the storage capacitors being formed vertically into the depth of a substrate in deep trenches. The test structure may enable a plurality of vertical FET selection transistors by a conductive electrode material embedded in an extended deep trench. With a test structure of this type, it is possible to evaluate characteristic values for leakage currents and capacitances at different semiconductor junctions and also between different sections of the integrated circuit arrangement and also to perform reliability stress tests.

REFERENCES:
patent: 5519236 (1996-05-01), Ozaki
patent: 5764569 (1998-06-01), Wright
patent: 6128219 (2000-10-01), Pio et al.
patent: 6339228 (2002-01-01), Iyer et al.

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