Test structure for electrical well-to-well overlay

Details Test structure for electrical well-to-well overlay Test structure for electrical well-to-well overlay

2005-07-26

2005-07-26

Schillinger, Laura (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S524000, C257S499000

Reexamination Certificate

active

06921946

ABSTRACT:
There is a test structure on a semiconductor substrate for testing misalignment between adjacent implanted regions of opposite conductivity in a semiconductor device. In an example embodiment, the test structure includes a first and a second triple well structure; the second triple well structure is adjacent to the first triple well-structure in a first direction. Each structure includes a lower buried n-well region, a p-well region, a p+-region, an n-well region and a base n+-region, wherein a central base portion and a central n-well region portion are common to the first and the second structure, with the central base portion as a symmetry line with a width. Between the central base portion and the p-well region in the first triple well-structure a first overlay, and between the central base portion and the p-well region in the second triple well-structure a second overlay is provided.

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