Test structure for determining a minimum tunnel opening size...

Details Test structure for determining a minimum tunnel opening size... Test structure for determining a minimum tunnel opening size...

2006-01-24

2006-01-24

Decady, Albert (Department: 2133)

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

Reexamination Certificate

active

06989551

ABSTRACT:
In one embodiment of the invention, a test structure far testing the sufficiency of tunnel opening sizes in a non-volatile memory cell includes N write paths aligned substantially in parallel, each of the write paths beings individually programmable and M floating gates, each of the floating gates overlapping each of the multiple write paths to form a N column-by-M row array of Intersecting areas. An N column-by-M row array of tunnel openings is formed in the intersecting areas and between the floating gates and write paths, with the tunnel openings in each array column being of a same size and the tunnel openings in each array row being of different sizes. A read path coupled to the M floating gates is operable to detect a programmed write path if the tunnel openings formed over the programmed write path are of sufficient size to successfully couple the M floating gates to the programmed write path.

REFERENCES:
patent: 4924278 (1990-05-01), Logie
patent: 5273923 (1993-12-01), Chang et al.
patent: 5323039 (1994-06-01), Asano et al.
patent: 6172392 (2001-01-01), Schmidt et al.
patent: 6208559 (2001-03-01), Tu et al.

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