Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed
Reexamination Certificate
2001-04-16
2003-09-09
Coleman, William David (Department: 2823)
Semiconductor device manufacturing: process
With measuring or testing
Electrical characteristic sensed
Reexamination Certificate
active
06617180
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method to detect and identify diagonal or horizontal bridging between two DRAM capacitors.
(2) Description of the Prior Art
Semiconductors typically comprise numerous and complex semiconductor devices in addition to electrical components such as capacitors, resistors, diodes and the like that function in cooperation with the semiconductor devices. The art has long known numerous interacting technologies and numerous semiconductor materials that are used to create semiconductor components. Applied for this purpose are processing steps such as depositing layers of material, the shaping of deposited layers by for instance creating openings or interconnect lines in conductive layers, creating regions of different conductivity by means of ion impurity implantation, creating surface regions of low-sheet resistivity for optimum connectivity, etc. For many of these processing steps optimum processing conditions are required. This not only for the creation of the desired device feature but to in addition assure that the semiconductor material that is used for the process is deposited in a controlled manner and without causing undesirable side effects, such as the occurrence of salicided stringers during the process of salicidation. One of the side-effects of a semiconductor processing steps is the diffusion of deposited materials into surrounding layers of dielectric, for instance the diffusion of a deposited layer of copper into surrounding Intra Level Dielectric. Methods are known in the industry to prevent such diffusion such as for instant the application of a barrier layer across the trench or opening into which the copper is deposited. The material of the barrier layer is selected such that the copper is prevented from diffusion from the opening into which the copper is deposited. Multiple techniques are further known to prevent undesired ion diffusion. As an example of this can be cited the creation of Lightly Doped Diffusion (LDD) regions adjacent to gate electrodes, which eliminate the effects of intense concentrations of electromagnetic fields in the interface between the gate electrode and the surface of the substrate over which the gate electrode is created. Metals, which have been deposited for the creation of interconnecting lines or contact plugs, is particularly prone to diffusion. Metal diffusion most readily results in disturbing the lattice structure of the surrounding semiconductor material, most particularly the silicon of the silicon substrate over which semiconductor devices and features are created. Further processing, which frequently requires high temperature processing, can further aggravate the crystalline disturbance, modifying relatively simple and concentrated imperfections to the level of crystalline disturbances that may have a serious negative effect on overall devices performance and reliability. Since these crystalline imperfections are in most cases not observable during the process of creating semiconductor devices, the device or a sub-component of the device must be tested either at intermittent points during the processing cycle or after the processing cycle has reached a phase where the process can be advantageously interrupted for device testing. In addition, testing may provide test results which are difficult to correlate with actual deficiencies in the semiconductor structure, which further makes it difficult to correlate particular processing steps with the results of the testing and with particular imperfections in the created device or device features. In view of the frequently extended period of time that is required to create more complex semiconductor devices, it becomes even more urgent to establish clear testing procedures that clearly identify particular and well identifiable device deficiencies and that further correlate the testing with processing steps that most likely are the cause of the device deficiencies.
The industry has over the years used a number of techniques to control the frequently extended processing sequence that is required to create semiconductor devices. It is unacceptable to create these devices in one uninterrupted processing stream without validating the process of the device creation at particular points before the device processing sequence is completed. This approach has been implemented by processing multiple wafers in one identical processing stream and by extracting at critical points within the processing stream one or more of these wafers for testing. It is clear that this approach is not commensurate with maximizing semiconductor device throughout, since the wafers that are extracted in this manner are frequently not re-joined with the main stream of wafer processing. Also, it is difficult to make the processing increment between the points where wafers are extracted small enough so that individual processing steps can be isolated and the therefrom potentially resulting device defects can be identified. If for instance two processing steps are applied, such as the deposition and etching of a layer followed by annealing at high temperatures the etched layer of semiconductor material, the heating step may be the essential cause and contributor to the device defect that is identified. The testing however at this stage does not necessarily identify the heating step as being the cause of the device defect. The process is further complicated by even minute variations in processing conditions, for instance variations in density or energy of ion impurity implantations or small variations in the thickness of a deposited layer of semiconductor material. Further complicating the process of device testing is the fact that semiconductor wafers have been increasing in size, this in order to create more semiconductor chips from one wafer thus reducing the cost per device.
Imperfections in a crystalline structure are most frequently created in regions of high stress within the structure or in regions where impurities have been introduced into the molecular structure of the crystal. Frequently these imperfections can be eliminated by high temperature annealing even though, if improperly applied, high temperature annealing can further aggravate the crystalline imperfection. High stress regions for instance are sharp transitions of one surface into another such as at the bottom of a trench that is created for Shallow Trench Isolation regions or trenches created for the creation of interconnect lines. Special processing steps are frequently required to eliminate these sharp transitions or to create, for instance, trench openings that have nearly vertical sidewalls.
Semiconductor devices and the functions that are performed by these devices can generally be divided into functions of data manipulation or logic functions and functions of data storage. Functions of data manipulation are mostly related to digital data manipulation but can also comprise functions of analog data manipulation. Functions of data storage provide data retention capabilities that are performed by semiconductor memory devices. Two types of memory devices can be identified, that is memory functions that retain data in storage cells from which the data can only be read (Read Only Memories or ROM's) and memory functions whereby the data cannot only be read but can also be altered (Random Access Memories or RAM's).
Random Access Memories memory devices are created using a number of different approaches. This results in creating different types of RAM devices such as the Dynamic RAM (DRAM) devices, which use capacitors as the storage medium and which are therefore, due to the non-permanent nature of the capacitive storage, periodically refreshed, and Static RAM (SRAM) devices, which depend on the presence of a power source for the retention of the stored data. DRAM memories offer advantages of economy of construction and of relatively high storage capabilities and have therefore attracted mo
Ackerman Stephen B.
Coleman William David
Saile George O.
Taiwan Semiconductor Manufacturing Company
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