Test structure for automatic dynamic negative-bias...

Details Test structure for automatic dynamic negative-bias... Test structure for automatic dynamic negative-bias...

2006-09-05

2006-09-05

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C331S057000

Reexamination Certificate

active

07103861

ABSTRACT:
The invention describes a novel test structure and process to create the structure for performing automatic dynamic stress testing of PMOS devices for Negative Bias Temperature Instability (NBTI). The invention consists of an integrated inverter, two integrated electronic switches for switching from stress mode to device DC characterization measurement mode, and a PMOS FET device under test (DUT). The inverter assures the proper 180 degree phase relationship between the test device source and gate voltage while the imbedded electronic switches provide isolation of the test device during DC characterization testing. Another embodiment of the invention enables the testing of multiple devices under test (DUT's).

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“Dynamic NBTI of p-mos Transistors and Its Impact on MOSFET Scaling”, G.Chan et al., IEEE Electron Device Letters, vol. 23, No. 12, Dec. 2002, pp. 734-736.
“Dynamic NBTI of PMOS Transistors and It's Impact on Device Lifetime”, G.Chen et al., Int'l Reliability Physics Symp. Proc. , Dallas TX, USA, pp. 196-202, Apr. 2003.

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