Test structure for a single-sided buried strap DRAM memory...

Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure

Reexamination Certificate

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Details

C257S296000, C257S301000, C257S905000, C257S908000, C257SE27097, C257SE27092

Reexamination Certificate

active

07126154

ABSTRACT:
A test structure for determining the electrical properties of a memory cell in a matrix-like cell array constructed on the basis of the single-sided buried strap concept has a connection between internal electrodes in the storage capacitors in two adjacent memory cells in the direction of the row of active regions in order to produce a series circuit. A first selection transistor and a first storage capacitor in a first memory cell and a second selection transistor and a second storage capacitor in a second memory cell, the active regions of the first and second selection transistors not being connected between the first and second selection transistors via a contact-making bit line.

REFERENCES:
patent: 6310361 (2001-10-01), Lichter
patent: 6339228 (2002-01-01), Iyer et al.
patent: 6459113 (2002-10-01), Morihara et al.
patent: 6469335 (2002-10-01), Hofmann
patent: 2002/0028550 (2002-03-01), Morihara et al.
patent: 2002/0195669 (2002-12-01), Morihara et al.

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