Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2003-05-30
2004-08-03
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S301000, C257S530000, C257S532000, C438S248000, C438S268000, C438S343000
Reexamination Certificate
active
06770907
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of stress-induced defect detection in semiconductor devices; more specifically, it relates to a system of devices and test methodologies for detecting stress-induced defects and to the use of particular of these devices as antifuses.
BACKGROUND OF THE INVENTION
The fabrication processes for silicon chips often lead to the formation of small stress-induced silicon defects that may coalesce into dislocations or stacking faults that degrade the product functionality, yield and reliability. Examples of such processes include ion implantation, trench isolation and other dielectric isolation processes, trench capacitor processes, oxidation processes in general and film deposition processes. Results of stress-induced defects include gate and capacitor dielectric leakage, which may be yield or reliability defects.
Semiconductor silicon substrates, being crystalline are subject to shearing of one portion of the crystal with respect to another portion of the crystal along a specific crystal plane. Dislocations, which are postulated as crystalline defects, occur in different types including: edge dislocations, screw dislocations and declinations.
In dynamic random access memory (DRAM) technologies employing deep trench storage capacitors, the leakage requirements for the capacitor are very stringent, and monitor systems are introduced for the detection of process induced defects in the active area of the DRAM deep trench storage capacitors.
While methods exists for monitoring processes for defects and other methods exist for detecting stress during processes development, an efficient and sensitive monitoring systems for detecting stress-induced defects that could be used for both development and routine monitoring in manufacturing is limited. Therefore, a method is needed to detect the formation of silicon defects that is sensitive, simple, applicable to process monitoring and process development and applicable to logic and DRAM technologies.
SUMMARY OF THE INVENTION
A first aspect of the present invention is a method for detecting semiconductor process stress-induced defects comprising: providing a polysilicon-bounded test diode, the polysilicon-bounded test diode comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region of an opposite dopant type from the diffused first region, the diffused first region surrounded by a peripheral dielectric isolation and a peripheral polysilicon gate comprising a polysilicon layer over a dielectric layer and the polysilicon gate overlapping a peripheral portion of the diffused first region; stressing the polysilicon-bounded test diode; and monitoring the stressed polysilicon-bounded test diode for spikes in gate current during the stress.
A second aspect of the present invention is a method for detecting semiconductor process stress-induced defects comprising: providing one or more polysilicon-bounded test diodes, each polysilicon-bounded test diodes comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region of an opposite dopant type from the diffused first region, the diffused first region surrounded by a peripheral dielectric isolation and a peripheral polysilicon gate comprising a polysilicon layer over a dielectric layer, the polysilicon gate overlapping a peripheral portion of the diffused first region; stressing each the polysilicon-bounded test diode; measuring during the stressing for each the polysilicon-bounded test diode, the current through the first region as a function of a forward bias voltage applied between the first and second regions at at least a predetermined forward bias voltage; and determining the frequency distribution of the slope of the forward bias voltage versus the first region current at the pre-selected forward bias voltage for the one or more polysilicon-bounded test diodes.
A third aspect of the present invention is a method for detecting semiconductor process stress-induced defects comprising: providing one or more polysilicon-bounded test diodes, each polysilicon-bounded test diode comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region of an opposite dopant type from the diffused first region, the diffused first region surrounded by a peripheral dielectric isolation, a peripheral polysilicon gate comprising a polysilicon layer over a dielectric layer, the polysilicon gate overlapping a peripheral portion of the diffused first region; stressing each the polysilicon-bounded test diode for a pre-determined amount of time; and monitoring, after the stressing, each the polysilicon-bounded test diode for soft breakdown.
A fourth aspect of the present invention is a method for detecting semiconductor process stress-induced defects comprising: providing a test DRAM, the test DRAM having a transfer device comprising a channel region between first and second P+ regions formed in a N-well in a silicon substrate and a gate formed over the channel region, the second P+ region electrically connected to a conductive core of a deep trench capacitor, the substrate acting as a second plate of the deep trench capacitor; stressing the test DRAM; and monitoring the stressed test DRAM for spikes in first P+ region current during the stressing.
A fifth aspect of the present invention is a method for detecting semiconductor process stress-induced defects comprising: providing a test DRAM, the test DRAM having a transfer device comprising a channel region between first and second P+ regions formed in a N-well in a silicon substrate and a gate formed over the channel region, the second P+ region electrically connected to a conductive core of a deep trench capacitor, the substrate acting as a second plate of the deep trench capacitor; stressing the test DRAM; and monitoring the stressed test DRAM for spikes in gate current during the stressing.
A sixth aspect of the present invention is a method for detecting semiconductor process stress-induced defects comprising: providing a test DRAM, the test DRAM comprising a transfer device comprising a channel region between first and second P+ regions formed in a N-well in a silicon substrate and a gate formed over the channel region, the second P+ region electrically connected to a conductive core of a deep trench capacitor, the substrate acting as a second plate of the deep trench capacitor; stressing each the test DRAM; measuring during the stressing, for the test DRAM, the current through the first P+ region as a function of a forward bias voltage applied between the first P+ region and the N-well at at least a pre-selected forward bias voltage; and determining the frequency distribution of the slope of the forward bias voltage versus the first P+ region current at the pre-selected forward bias voltage for the one or more test DRAMs.
A seventh aspect of the present invention is a method for detecting semiconductor process stress-induced defects comprising: providing a test DRAM, the test DRAM comprising a transfer device comprising a channel region between first and second P+ regions formed in a N-well in a silicon substrate and a gate formed over the channel region, the second P+ region electrically connected to a conductive core of a deep trench capacitor, the substrate acting as a second plate of the deep trench capacitor; stressing the test DRAM for a pre-determined amount of time; and monitoring, after the stressing, each the test DRAM for soft breakdown.
An eighth aspect of the present invention is a method of fabricating an antifuse comprising: providing a silicon substrate having a surface; forming a ring of shallow trench isolation having an inner and an outer perimeter in the substrate extending from the surface of the substrate into the substrate; forming a polysilicon gate overlapping the inner perimeter of the shallow trench isolation on the surface of the substrate, the poly
Abadeer Wagdi W.
Adler Eric
Brown Jeffrey S.
Gauthier Jr. Robert J.
McKenna Jonathan M.
Nelms David
Nguyen Dao H.
Walsh Robert A.
LandOfFree
Test structure and methodology for semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Test structure and methodology for semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test structure and methodology for semiconductor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3336643