Test signal generator for semiconductor integrated circuit memor

Details Test signal generator for semiconductor integrated circuit memor Test signal generator for semiconductor integrated circuit memor

1990-04-10

1991-06-04

Clawson, Jr., Joseph

Static information storage and retrieval

Read/write circuit

Testing

365190, 371 101, 371 211, G16C 2900

Patent

active

050220071

ABSTRACT:
A test signal generator for a semiconductor integrated circuit memory, wherein when transfer transistors (20, 21, 14, 15) are rendered conductive, a test data cloumn is supplied from an I/O line pair (11, 12) to a column of a register (10) and stored therein. When a transfer (67) is rendered conductive, the test data column written in the register is written in a column of a memory cell (22) in the same pattern and when transfer transistors (16, 17) are rendered conductive, the test data column written in the register is inverted and the, written in the memory cell column, Data in the memory cell column is read out by a word line (13) and amplified by a sense amplifier (5), so that the data and the test data stored in the register are compared by a coincidence detection circuit 8 to detect whether it is coincident or not.

REFERENCES:
patent: 4833643 (1989-05-01), Hori
patent: 4856002 (1989-08-01), Sakashita et al.
patent: 4980863 (1990-12-01), Ogihara
Inoue et al., "Parallel Testing Technology VLSI Memories", International Test Conference (1987) pp. 1066-1071.
Ohsawa, et al., "Special Purpose Accelerators", IEEE International Solid-State Circuit Conference (1987), pp. 286-287.
Arimoto et al., "A 60ns 3.3V 16Mb DRAM", IEEE International Solid-State Conference (1989) pp. 244-245, 352.

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