Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2005-07-26
2005-07-26
Torres, Joseph D. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S201000
Reexamination Certificate
active
06922800
ABSTRACT:
A method for improving the efficiency of test sequences for circuits with embedded multiple-port arrays, such as random access memory (RAM), is described, With existing test generation methods, it is a common occurrence that a resulting test sequence only utilizes a minimum number of read ports for detecting a target fault. When this type of test sequences is applied, one or more outputs of embedded RAMs may not attain known values, consequently reducing the effectiveness of the test sequences. The present invention enhances test sequences to that when they are applied, all outputs of embedded RAMs attain known values.
REFERENCES:
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Chen Xinghao
Watkins Joseph C.
Cadence Design Systems Inc.
Orrick Herrington & Sutcliffe LLP
Torres Joseph D.
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