Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2000-10-26
2003-09-09
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S201000
Reexamination Certificate
active
06618826
ABSTRACT:
TECHNICAL FIELD
This invention is related to testing integrated circuit, and more particularly to a method for improving the efficiency of test sequences intended for testing circuits having a plurality of multi-port RAMs embedded in logic.
BACKGROUND OF THE INVENTION
In the last few decades there has been a drastic development in the field of microelectronic, particularly in the field of integrated circuits. Circuit density in the order of hundreds of millions of interconnected circuits has prompted the introduction of new techniques for automatically designing and testing the integrated circuits. In today's environment, with the advent of VLSI (Very Large Scale Integration) and ULSI (Ultra Large Scale Integration) it is imperative more than ever that a chip to be manufactured be designed without any error. It is just as important that such chips be tested thoroughly and easily to weed out any defective chip.
Techniques for testing integrated circuits have evolved over the years, and the impact of testing on the chip design has grown in importance. It is no longer possible to design an integrated circuit chip without due consideration of its testing aspect. This approach is known as Design for Testability.
A difficult problem encountered while making a chip ever more testable is a trend in industry to merge logic and memories onto a single chip. The problem is further complicated by the logic surrounding the memory from all sides; hence, its name embedded memory or array. Techniques had to be developed to account for this trend, which prompted the introduction of scan designs, well known in the art. By placing scan chains at the boundaries between the logic and the embedded arrays, it is possible to segregate the logic from the memory in order that they be tested separately. have evolved over the years from stand-alone to embedded and from single port to multi-port arrays. A typical architecture of a circuit with an embedded multi-port memory is illustrated in FIG.
1
.
A multi-port RAM embedded in logic (
40
) is typically provided with multiple write/reset ports and multiple read ports, each capable of accessing either a section or the entire storage space of the RAM. A simple conventional RAM is provided with a write port formed by a plurality of address pins (Ao, . . . , Aj), a plurality of data pins (Do, . . . , Di) equal to the word length, and a write clock pin (W_clk), serving as inputs. A bank of setup latches (
30
) controls the address and input data pins of the embedded RAM through combinatorial logic blocks (
25
). A pulse on the write clock pin (W_clk) of the RAM stores data on the input data pins (Do, . . . , Di) at a word location specified by the address pins (Ao, . . . , Aj). (For sake of simplicity, timing-related issues such as hold time unless specifically pointed out will be ignored). A read port, on the other hand, includes a plurality of address pins (Ao, . . . , Aj) and a read-enable pin (R_en) as its inputs, and a number of data output pins (Do, . . . , Di) equal to the word length. When a read port is read-enabled, the bit values of the word selected by the address on the read port address pins become available at the output data pins and are latched in read-capture latches (
10
) by a subsequent pulse on the read-capture clock. When the read port is read-disabled, the output pins take a so-called read-off value which depends on the physical design of the RAM for a specific technology. The read-off value is either a logic 0, 1, or X (i.e., a condition wherein neither a logic 1 nor a 0 is guaranteed).
Still referring to
FIG. 1
, logic (
40
) is provided with a plurality of input pins (Plo, . . . , Plp) and clock signal pins (CLKo, . . . , CLKk) as primary inputs, and plural output pins (POo, . . . , POq) as primary outputs. The clock distribution and gating logic (
15
) prompt clocks (CLKo, . . . , CLKk) and a subset of the inputs (Plo, . . . , Plp) to generate control signals to activate the setup latches (
30
), the write clock pins (W_clk) of the RAM's write ports, the read-capture signals to the read-capture latches (
10
) and local clocks regulating the sequential elements (
20
).
Oftentimes, combinatorial logic as well as sequential elements (
20
) are present in the ‘upstream’ and ‘downstream’ logic from the embedded RAM. Circuits using multiple clocks (e.g., CLKo, . . . , CLKk) are provided with a clock distribution and gating logic (
15
) that includes sequential elements as well. Other circuits, having combinatorial logic blocks (
25
), are positioned between the setup latches (
30
), the embedded multi-port RAM and the read-capture latches (
10
).
In a full scan design, as illustrated in
FIG. 2
, an embedded RAM is directly controlled by the setup latches (
30
, in
FIG. 1
) and read-capture latches (
10
, in
FIG. 1
) which are configured as scan latches (
50
). Typically, they are linked to form a chain (or chains) for scan shift (load and unload) operations. The scan-load operation sets the scan latches to the desired values and the scan-unload shifts out the values stored in the latches.
In a partial-scan design, as illustrated in
FIG. 3
, the setup latches (
30
, in
FIG. 1
) are configured as scan latches (
50
) directly controlling the data and address inputs of the RAM, except for the read-capture latches (
10
, in FIG.
1
). In a non-scan design, all the latches and memory elements are configured in a non-scannable configuration and are not directly accessible through the primary inputs and outputs.
A write/read port must have as its inputs a plurality of address pins, a plurality of data input pins equal to the word length, a write clock pin and a read enable pin, and a plurality of data output pins equal to the word length as its outputs.
A write/read port combines the functions of a write port with those of a read port, using a single set of address input pins. When a pulse appears at the write clock pin while the port is read-enabled, data on the data input pins becomes available at the output pins during and after the write clock pulse, provided that the port is still read-enabled while the address inputs remain unchanged. Such an operation is commonly referred to as write-through mode. It can also be advantageously configured having separate write and read ports.
A reset port has as inputs a plurality of data input pins equal to the word length and a write clock pin. During and following a pulse being applied to the write clock pin of a reset port, data on the input pins is written into all words in the RAM. When more than one write/reset port attempts to simultaneously write on the same word, it is customary that the design and technology dictate that one of the ports dominate the write operation. Accordingly, the bits that prompt the two simultaneous write operations attempting to write different values are set in a predetermined manner. In the present model, the dominant port always appears before the dominated port(s). When such specification is not available from the designer and/or technology sources, unknown values are assumed for the bits having conflicting values on simultaneous writes. A RAM provided with a read-capture built-in capability holds the read data available at the output pins until the next read operation is performed. Such a RAM configuration is commonly referred to as read-hold.
DETERMINISTIC TEST PATTERN GENERATION
Referring now to the test circuits that include (an) embedded RAM(s), it is known in the art that in a conventional deterministic automatic test pattern generation (ATPG), a target fault is selected for processing in the upstream or downstream logic from the embedded RAM, including at the input and output pins of the RAM. A test sequence is then generated if the target fault is testable. This test sequence is transferred to another process, referred to as test subsumation, which identifies similar test sequences and merges them into one. Test sequences resulting from the subsumation process are significantly more compact, with unspecified input pins filled with random values,
Chen Xinghao
Watkins Joseph C.
Cadence Design Systems Inc.
De'cady Albert
Orrick Herrington & Sutcliffe LLP
Torres Joseph D.
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