Test results checking via predictive-reactive emulation

Details Test results checking via predictive-reactive emulation Test results checking via predictive-reactive emulation

1999-03-23

2001-12-18

Iqbal, Nadeem (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C703S014000

Reexamination Certificate

active

06332201

ABSTRACT:

THE FIELD OF THE INVENTION
The present invention relates to digital systems, and, more particularly to an apparatus and method for verifying the behavior of a digital system, where the digital system can exhibit several differing but valid behaviors from the same input vector.
BACKGROUND OF THE INVENTION
Simulating the behavior of digital systems can often produce ambiguous results. That is, for the same input, the digital system can exhibit several behaviors, all of which are equally valid and in accordance with the specifications. The behavior chosen by the system is a mere idiosyncrasy of the implementation.
One solution for dealing with ambiguous simulation results is the development of a very precise model of the digital system and tight checks on the expected results. The disadvantage of developing a very precise model arises when the system complexity escalates, or the system design evolves from its original definition. Maintaining such a precise model in the face of increased design complexity and a multitude of design changes results in a considerable development and maintenance effort.
Another solution for dealing with ambiguous simulation results is the development of a less stringent model of the digital system, and a looser set of rules to check the results. The disadvantage of developing a less stringent model is that with time, the model diverges from the actual system, and the rules to check the results become increasingly looser, until the model/rules become over-permissive and allow potential defects to slip through. This is especially true for complex concurrent systems with multiple simultaneous activities underway in different states of progress, such as a pipelined digital computer system.
In yet another solution, portholes are introduced into the model of the digital system in order to examine critical states that dictate the eventual outputs produced by the system. The disadvantage of this solution is that it only works in a simulation environment where the state is accessible. However, a digital system can not normally tolerate such an invasive internal examination. Moreover, for increasingly complex systems, the porthole method can be carried to an extreme that leaves the effort to check the design very tightly wed to the system being tested. Thus, the checker loses its independence in providing a valid check of the design in question.
In view of the above, there is a need for a functional testing system which allows the flexibility of building a relatively loose hardware emulator of a digital system, yet provides tighter checking through a set of pre-defined behavioral rules applied to the outputs of the hardware emulator of the digital system.
SUMMARY OF THE INVENTION
The present invention provides a functional testing system for verifying the behavior of a digital system. The functional testing system includes a plurality of input vectors, a hardware model representing a relatively low-level software characterization of the digital system, and a hardware emulator representing a relatively high-level software characterization of the digital system. The functional testing system also includes a system simulator for applying the plurality of input vectors to the hardware model and the hardware emulator, such that each input vector applied to the hardware model produces a corresponding model output vector, and each input vector applied to the hardware emulator produces one or more corresponding emulator output vectors. The functional testing system further includes a comparator for comparing each of the hardware emulator output vectors to the model output vector. If the model output vector matches one of the emulator output vectors, a match signal is activated and a current matching output vector is provided. The functional testing system also includes a history file for storing matching output vectors from the comparator, and a set of context specific rules defining a valid behavior for the list of matching output vectors stored in the history file. Finally, the functional testing system includes a rules checker which determines whether the current matching output vector is valid based on the history file, internal model state information from the hardware emulator, and the set of context specific rules.
In one embodiment, the context specific rules include rules on output ordering, output persistence, and data checking. In one embodiment of the present invention, the system simulator includes a separate model simulator for simulating the hardware model, and a separate predictive simulator for simulating the hardware emulator. In another embodiment of the present invention, if the comparator determines that there are no current matching output vectors between the hardware emulator and the hardware model for a given input vector, an exception is raised and the verification is terminated. If the rules checker determines that the current matching output vector is invalid, an exception is raised.
The present invention also provides a method for verifying the behavior of a digital system. The method begins by defining a hardware model representing a relatively low-level software characterization of the digital system. A hardware emulator is also defined representing a relatively high-level software characterization of the digital system. Next, a plurality of input vectors are defined. The hardware model and the hardware emulator are then simulated with a system simulator by applying the plurality of ordered input vectors to the hardware model and the hardware emulator. Each input vectors applied to the hardware model produces a corresponding model output vector, and each input vector applied to the hardware emulator produces one or more corresponding emulator output vectors. Next, each of the one or more emulator output vectors produced by the hardware emulator is compared to the model output vector. If the model output vectors matches one of the one or more emulator output vectors, a match signal is activated, a current matching output vector is provided, and the current matching output vector is stored in a history file. A set of context specific rules is then defined which describe a valid behavior for the ordered list of matching output vectors stored in the history file. Finally, the method determines whether the current matching output vector is valid based on the history file, the internal model state information from the hardware emulator, and the set of context specific rules.
The present invention further provides a computer readable medium containing instructions for controlling a computer system to verify the behavior of a digital computer system.
The present invention offers the advantage of a functional testing system which allows relatively loose hardware emulation of a digital system, yet provides tighter checking through a set of pre-defined behavioral rules applied to the outputs of the hardware emulator of the digital system.


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