Test patterns for measurement of effective vacancy diffusion...

Details Test patterns for measurement of effective vacancy diffusion... Test patterns for measurement of effective vacancy diffusion...

2006-07-11

2006-07-11

Tran, Minhloan (Department: 2826)

Semiconductor device manufacturing: process

With measuring or testing

C438S011000, C438S018000, C257S048000, C324S765010

Reexamination Certificate

active

07074629

ABSTRACT:
A test pattern (100, 200, 300, 400, 600, 700) has a first metal structure (102) disposed on a substrate (352), one or more intermediate layers (358) disposed above the first metal structure (102) and a second metal structure (104) disposed above the one or more intermediate layers (352). A first via (106) passes through the intermediate layers (352) and connects the first metal structure (102) to the second metal structure (104). One or more third metal structures (108) are disposed above the one or more intermediate layers (352) and the first metal structure (102). One or more second vias (110) pass through the intermediate layers (352) and connect the first metal structure (102) to the third metal structures (108). The second vias (110) are located outside of a radius (R) from a center of the first via (106). The third metal structures (110) are separated from the second metal structure (104) by a dielectric material (366).

REFERENCES:
patent: 6194739 (2001-02-01), Ivanov et al.
patent: 6577149 (2003-06-01), Doong et al.
Ogawa, E.T., et al, “Stress-Induced Voiding under Vias Connected to Wide Cu Metal Leads,” IEEE International Reliability Physics Symposium Proceedings, 40thAnnual, 2002, pp. 312-321.

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