Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2001-03-26
2004-07-20
Baderman, Scott (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S037000, C714S741000
Reexamination Certificate
active
06766473
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a test pattern selection apparatus, method and program for selecting a test pattern based on fault detection information acquired by employing a fault simulation from among a plurality of functional verification patterns relevant to an LSI or a functional block inside the LSI. In particular, the present invention pertains to a technique that makes it possible to achieve a fault coverage (fault detection rate) that is substantially identical to a value that can be expected in all functional verification patterns with functional verification patterns in number substantially fewer than the all functional verification patterns.
2. Description of the Related Art
In general, for each of the chips of manufactured LSIs, a shipment test (quality test) is carried out to check (select only conformance) prior to shipment that such LSIs are not faulty by employing test patterns that conveniently use and edit a plurality of verification patterns used for functional verification during development. In such shipment test, it is required that faults in LSI chips can be detected as reliably as possible by used test patterns. Thus, a fault coverage obtained by fault detection information extracting processing whose main means is fault simulation, a value of which is recognized to have a strong correlation with a product quality from the viewpoints of experience, is employed as a criterion to determine whether or not a test pattern can detect faults reliably. The “fault coverage” used here is a value that indicates how well faults can be detected with test patterns, for example, such as single stuck-at faults assumed in an LSI of a gate level description, in which basic cells composed of combinational logic gates (including primitive elements) and more complicated cells such as flip-flops are connected to each other. Each of the stuck-at faults, assumed 2× number of connection nodes in total in an LSI, is defined for each connection node (wiring) to be fixed to 0 or 1.
In the meantime, although this fault coverage can be directly obtained by fault simulation employing verification patterns, in general, enormous CPU resources are required for fault simulation employing verification patterns. Moreover, in recent years, with advancement of large-scaled and complicated LSIs, the size of verification patterns (number of steps) rapidly increases. Further, it is essential to restrict the size of test patterns that can be stored in an LSI tester in order to carry out a shipment test at a reasonable cost. Thus, it becomes difficult to use such verification pattern intact as test patterns. At the present, it is indispensable to substantially reduce the number of verification patterns used as test patterns.
From such background, conventionally, there has been employed an approach that an LSI developer or function verification engineer selects verification patterns with a possible high fault coverage in consideration of the contents of verification patterns from among all verification patterns; checks the fault coverage for each pattern relevant to faults randomly sampled at a low rate by using such all verification patterns, and selects verification patterns with its high fault detection rate. However, there has been a problem that this approach is poor in efficiency and poor in reliability. In contrast, recently, as an efficient and reliable method, there are commercially available a functional verification coverage evaluation apparatus for analyzing how well verification patterns composed of a number of individual verification patterns achieves functional verification coverages (code coverages) relevant to RTL (Register Transfer Level) description of an LSI or a functional verification pattern selection apparatus for selecting a minimum number of verification pattern sets that achieve the same functional verification coverages as all verification patterns by using the result obtained for each verification pattern. (There are a few items for evaluating quality of functional verification. Consequently a few functional verification coverages are defined.) The result of the selection is used for shipment test pattern selection.
Here, test pattern selection processing employing such functional verification coverage evaluation apparatus and functional verification pattern selection apparatus will be briefly described with reference to FIG.
1
.
In conventional test pattern selection processing, when a target LSI or RTL net
50
of a functional block in the LSI and verification patterns (in general, a set of a number of verification patterns)
51
are inputted to a test pattern selection apparatus
40
, an RTL code coverage evaluation tool
41
extracts and outputs the functional verification coverages for each verification pattern. Then, a verification pattern selection tool
42
makes selections sequentially from a verification pattern with its high coverage relevant to functional verification items targeted for selection. In addition, this selection tool selects a minimum number of test patterns that achieves functional verification coverages equal to those of all test (verification) patterns. Lastly, when selected verification patterns
52
, a net
53
at a gate level that corresponds to an RTL net
50
of the targeted LSI, a library
54
of a basic cell employed in the net
53
, and an undetected fault list
55
(in general, automatically prepared by a fault simulator) before fault detection information extraction presumed relevant to the net
53
are inputted to a fault simulator
43
, thereby carrying out fault detection information extraction (fault simulation), a fault coverage indicating how well faults can be detected by (a set of) the verification patterns and an (undetected) fault list
56
is outputted. In this case, fault simulation employing individual verification patterns is executed for a (undetected) fault list of the results of fault simulation employing the previous verification patterns. Hereinafter, this simulation is referred to as “incremental” fault simulation (fault detection information extracting processing) distinctly in particular.
According to such test pattern selection processing, in spite of a set of verification patterns that are significantly small as compared with all verification patterns, there can be obtained a fault coverage comparatively close to an expected fault coverage in the case where the full verification patterns are employed. This makes it possible to significantly reduce a CPU time required for extracting fault detection information relevant to an LSI below a gate level or a test pattern length at the time of shipment test.
However, such conventional test pattern selection processing has the following technical problems to be solved.
That is, the functional verification coverages obtained by the conventional test pattern selection processing activates functional verification items at the RTL description level of a targeted LSI in strict senses. The functional verification coverages are good indicators for the coverage of controllability in testability that is s scale indicating how reliably shipment test can be carried out in gate level description. However, the functional verification coverages are not always reliable as to observability. Even although the number of verification patterns can be significantly reduced, in the case where an attempt is made to ensure a fault coverage almost equal to that of all verification patterns, the fault coverage is effective as a first solution, but is somewhat lower (by some percents) than a fault coverage which would be obtained in all verification patterns.
In general, the analysis of undetected faults and preparation of additional verification patterns are difficult works requiring many engineer resources. Thus, the slight lowering of fault coverage is a very big problem. Therefore, it is expected to introduce a test pattern selection technique with its high efficiency capable of reliably achieving a fault coverage that is su
Baderman Scott
Kabushiki Kaisha Toshiba
Lohn Joshua A
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