1995-05-12
1996-11-12
Canney, Vincent P.
Excavating
39518306, G01R 3128
Patent
active
055747329
ABSTRACT:
A test pattern generator accompanying digital integrated circuits for successively generating a plurality of test patterns for a built-in self test. A plurality of shift registers are serially connected in a loop for successively outputting the test patterns in response to a clock signal. At least one logic gate is connected among the shift registers. At least one control means is connected within the loop. Using such a configuration, the shift registers are set to an initial pattern. The shift registers are then set to one of a plurality of test patterns. The test patterns are then successively output through the shift registers in response to the clock signal.
REFERENCES:
patent: 5090035 (1992-02-01), Murase
patent: 5187712 (1993-02-01), Malleo-Roach et al.
Hsieh Cheng-Ju
Pan Chien-Chung
Canney Vincent P.
United Microelectronics Corporation
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