Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
1999-03-02
2002-06-11
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S049000, C257S050000
Reexamination Certificate
active
06403978
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to an improved test pattern that is monitored to measure critical dimensions of patterns formed during the fabrication of semiconductor devices.
(b) Description of the Related Art
Photolithographic technology is generally used to form patterns on semiconductor devices. A master photomask is made using an electron beam exposure system; then its image is reciprocated on a wafer by optical printers. Exposing radiation is transmitted through a clear part of a mask. An opaque part of the circuit pattern blocks some of the radiation. A resist, which is sensitive to the radiation and has resistance to the etching, is coated on the wafer surface. The mask is aligned within a required tolerance on the wafer; then radiation is applied through the mask, the resist image is developed, and a layer underneath the resist is etched.
The wafer comprises a plurality of chip regions each having a predetermined circuit design in matrix formation and a plurality of scribing regions defining the chip regions. Each chip region comprises several active regions and device isolation regions, with a plurality of devices being formed on the active regions. Each scribing region has alignment marks for aligning critical dimension bars of a pattern on the chip.
The critical dimension bars of the chip pattern can undergo alteration as a result of exposure and etch process conditions, and by proximity effect caused by an arrangement of the critical dimension bars. To be able to detect these alterations, a test pattern is formed identical to that of the chip pattern, and is formed using the same etch and photolithographic method. Accordingly, the variations in the critical dimension bars of the chip pattern can be measured indirectly by detecting the change in the test pattern on the scribing region.
As shown in
FIG. 1
, the prior art test pattern comprises a plurality of critical dimension bars
3
and
3
′ respectively arranged in horizontal and vertical directions on a silicon wafer. The critical dimension bars
3
and
3
′ are formed having different lengths, densities and widths, because the effects given by light or gas during exposure and etch processes are variable according to the formation of a test pattern mask.
However, since the critical dimension bars
3
and
3
′ of this test pattern are arranged only on a plane surface of a substrate, the measurement of variations in the critical dimension bars of the chip pattern on other non-planar areas such as a step portion is difficult. That is, the critical dimension bars of the chip pattern are formed not only on active regions but also extended over a device isolation region or inter-layer isolation region formed having a step portion with an active region. Accordingly, it is impossible to measure the variations of the chip pattern on the surface of stepped portions using this test pattern.
SUMMARY OF THE INVENTION
In accordance with the present invention, an improved test pattern is formed in the same manner as the patterns on the chip region so as to precisely monitor the variations of patterns on the chip region.
To achieve this result, the test pattern comprises a first region as an active region of a semiconductor device and a second region as a device isolation region around the first region. The second region, which is formed on a substrate, includes a stepped layer that is different in height from the first region. A plurality of parallel critical dimension bars are provided across the first and second regions.
The stepped layer may be an oxide layer formed at the same time when a device isolation oxide layer is formed on the chip region.
Accordingly, the critical dimension bars of the test pattern according to the present invention have a similar configuration with the critical dimension bars of the pattern on the chip region.
REFERENCES:
patent: 5179433 (1993-01-01), Misawa
patent: 5780870 (1998-07-01), Maeda
patent: 6028324 (2000-02-01), Su
patent: 6143579 (2000-11-01), Chang
patent: 0562309 (1993-09-01), None
Chaudhuri Olik
Citicorp USA, Inc.
Ha Nathan W.
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