Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2001-12-28
2004-05-11
Pert, Evan (Department: 2829)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C438S018000
Reexamination Certificate
active
06734458
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a test pattern for measuring a contact resistance and method of manufacturing the same, and more particularly to, a test pattern for measuring a contact resistance and method of manufacturing the same, capable of easily measuring a contact resistance in a semiconductor device using a self-aligned line contact.
2. Description of the Prior Art
In general, as the integration level of semiconductor devices, the contact area becomes narrow. As the contact area is narrowed, there is a problem that the contact resistance is increased due to defective contact. Therefore, in order to confirm that the contact resistance suitable for the semiconductor device before an actual process for manufacturing the device is performed, a test pattern for measuring a contact resistance is manufactured depending on a design rule of a contact actually applied to a device and the contact resistance is measured using the manufactured test pattern for measuring a contact resistance.
FIG. 1
is a structure of a test pattern for measuring a conventional contact resistance.
Referring now to
FIG. 1
, a plurality of device isolation structures
12
are formed in a test wafer
11
to define a plurality of active regions. After word lines (not shown) are formed, a plurality of source/drain diffusion layers
13
are formed by source/drain ion implantation process. An interlayer insulating film (not shown) and a contact hole (not shown) are formed on the entire structure in which the plurality of the source/drain diffusion layers
13
are formed. A contact pattern
14
is formed within the contact hole. Two contact patterns
14
are formed in every source/drain diffusion layer
13
. Then, an interconnection pattern
15
for electrically connecting the plurality of the source/drain diffusion layers
13
is formed.
A series of a process of manufacturing a test pattern for measuring a contact resistance is performed based on a design rule of a process of manufacturing an actual device.
As shown in
FIG. 1
, in the conventional test pattern for measuring a contact resistance, two isolated contact patterns
14
are formed in a single isolated source/drain diffusion layer
13
and the interconnection pattern
15
is formed in the two contact patterns
14
, respectively, so that it can be connected to neighboring another contact pattern
14
. A flow of current necessary to measure the contact resistance has a two-dimensional current flow in order of the interconnection pattern
15
, the contact pattern
14
and the source/drain diffusion layer
13
, as a current path
16
shown in FIG.
1
.
An ideal total resistance, when the contact pattern
14
preferably contacts the source/drain diffusion layer
13
, can be easily found by a general mathematic equation. If the total resistance obtained by the test pattern for measuring a contact resistance is similar to the ideal total resistance, a design rule for manufacturing an actual device is applied. If the total resistance obtained by the test pattern for measuring a contact resistance is higher than the ideal total resistance, it is assumed that a defective contact is generated. Thus, a new design rule is applied or another solution is considered. As such, defective devices can be prevented in advance and unnecessary time and cost could be reduced, by allowing the test pattern for measuring a contact resistance to in advance diagnose a possible problem that can be generated in an actual device.
Recently, a semiconductor device using a self-aligned line contact is formed. However, the contact resistance of the semiconductor device could not be measured using the conventional test pattern for measuring a contact resistance. In other words, the conventional test pattern for measuring a contact resistance is suitable to measure the contact resistance of the device having an isolated source/drain diffusion layer and an isolated contact pattern but is not suitable to measure the contact resistance of a device having a self-aligned line contact.
A flash EEPROM as a semiconductor device using the self-aligned line contact will be below described as an example. A plurality of device isolation structures are first formed to define a plurality of active regions. Word lines surrounded by a spacer insulating film are then formed and a source/drain diffusion layer is formed. Next, an interlayer insulating film is then deposited and flattened. A self-aligned contact hole through which the plurality of the source diffusion layers are exposed is formed by a self-aligned source contact process and the self-aligned contact is filled with a conductive layer to form a source line contact.
As such, the source line contact connects the plurality of the source diffusion layers into one. Therefore, if a two-dimensional current flow is generated as in a prior art, current flows along the line contact made of a conductive material of a low resistance but current does not flow into the source diffusion layer formed by ion implantation process. Thus, it could not be seen that defective contact occurred in respective source diffusion layers.
Considering advantages that allows the test pattern for measuring a contact resistance to diagnose in advance problems generated in an actual device to prevent defective devices in advance and to reduce unnecessary time and cost, there is a need for a test pattern for measuring a contact resistance suitable for a semiconductor device using the self-aligned line contact.
SUMMARY OF THE INVENTION
The present invention is contrived to solve the above problems and an object of the present invention is to provide a test pattern for measuring a contact resistance and method of manufacturing the same, capable of easily measuring a contact resistance in a semiconductor device using a self-aligned line contact.
In order to accomplish the above object, a test pattern for measuring a contact resistance according to the present invention, is characterized in that it comprises a test wafer in which a plurality of device isolation structures are formed to define a plurality of active regions; a plurality of interconnection diffusion layer formed in a word line region crossing the plurality of the device isolation structures and the plurality of the active regions; a plurality of source diffusion layers formed in a first line contact region located at one side of the word line region; a plurality of source diffusion layers formed in a second line contact region located at the other side of the word line region; and a plurality of line contact pattern formed in the first and second line contact regions, wherein the line contact pattern formed in the first line contact region and the line contact pattern formed in the second line contact region are alternately positioned and wherein current for measuring a resistance flows along the first line contact region and the second line contact region between the word line in a three-dimensional manner.
A method of manufacturing a test pattern for measuring a contact resistance according to the present invention, is characterized in that it comprises the steps of forming a plurality of device isolation structures in a test wafer to define a plurality of active regions; performing an impurity ion implantation process to simultaneously form a source diffusion layer in a plurality of active regions of a first line contact region, an interconnection diffusion layer in a plurality of active regions of a word line and a source diffusion layer in a plurality of active regions of a second line contact region; forming a word line surrounded by an insulating film spacer in the word line region; forming an insulating layer the surface of which is flattened on the entire structure including the word line; forming a self-aligned contact mask on the insulating layer; and forming a plurality of line contact patterns in the first and second line contact regions through a self-aligned contact process using the self-aligned contact mask, wherein the line contact pattern
Kim Ki Seog
Lee Keun Woo
Park Sung Kee
You Young Seon
Morgan & Lewis & Bockius, LLP
Pert Evan
LandOfFree
Test pattern for measuring contact resistance and method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Test pattern for measuring contact resistance and method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test pattern for measuring contact resistance and method of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3187316