Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2000-11-03
2003-05-06
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C324S716000, C324S765010, C324S762010, C324S671000, C355S133000, C438S018000
Reexamination Certificate
active
06559475
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a test pattern for evaluating a process of silicide film formation.
2. Description of the Background Art
Generally, a logic circuit must be operated at a high speed. To satisfy this high speed characteristic, silicide or polycide is used as a wiring material for a semiconductor device. For example, polycide (structure in which a silicide layer is stacked on the a polysilicon layer) wiring can be employed to a gate electrode of a transistor constructing the logic circuit, and a silicide layer can be formed on the top surface of a source/drain. Therefore, the inventor of the present invention became interested in a test pattern for evaluating a process of silicide or polycide film formation and a method thereof. Although many conventional methods for evaluating a process of metal or polysilicon wire formation are known, any techniques for evaluating a process of silicide film formation are not known.
Next, a conventional test pattern for evaluating a process of conductive wire formation and a method thereof will be described.
Firstly,
FIG. 1
illustrates a van der Pauw cross resistor pattern well-known as a test pattern for measuring the sheet resistance Rsh. The van der Pauw cross resistor pattern for measuring the sheet resistance is disclosed by Buehler, M. G., Grant, S. D., and Thurber, W. R., “Bridge and van der Pauw Sheet Resistors for Characterizing the Line Width of Conducting Layers,” in J. Electrochem. Soc., Vol. 125, No. 4 (April 1978), which is used by a number of semiconductor manufacturers in order to evaluate the characteristics of a conductive line. As illustrated therein, a cross resistor pattern
100
is constructed from two rectangular conductive layers that intersect at right angles. The rectangular conductive layers
110
and
120
each have a width (a), and a length(b) about twice the width. The portion at which a first conductive layer
110
extended in a longitudinal direction and a second conductive layer
120
extended in a horizontal direction perpendicular to the first conductive layer
110
intersect is a central portion
130
, and the sheet resistance is the resistance of the central portion
130
whose horizontal and longitudinal sides have the same length (a). One end of the first and second conductive layers
110
and
120
is connected to current contact pads I
1
and I
2
by conductive taps
110
a
and
120
a
, respectively. In addition, the other end of the first and second conductive layers
110
and
120
is connected to voltage contact pads V
1
and V
2
by the conductive taps
110
b
and
120
b
, respectively.
In the cross resistor pattern of
FIG. 1
, the sheet resistance Rsh can be obtained by measuring the voltage variance between the voltage contact pads V
1
and V
2
, after applying an already known current through current contact pads I
1
and I
2
.
FIG. 2
illustrates a bridge resistor pattern. The bridge resistor pattern
200
, having a conductive strip
210
and square current contact pads Ia and Ib each connected to both ends of the conductive strip
210
, is formed in a dog bone shape. In addition, voltage contact pads Va and Vb are electrically connected to the lateral ends of the conductive strip
210
through conductive taps
220
a
and
220
b.
The width (W) of the conductive strip
210
is preferably the same as the length (a) of the horizontal and longitudinal sides of the central portion of the sheet resistor test pattern
100
of FIG.
1
. In addition, the length of the conductive strip
210
can be varied. The resistance Rdb of the conductive strip
210
can be calculated by measuring the voltage difference between the voltage contact pads Va and Vb while applying a known current through the current contact pads Ia and Ib. The above-mentioned resistance is a resistance corresponding to the length (L) between the two voltage contact pads Va and Vb.
By forming a plurality of test patterns of different lengths (L), the reliability of evaluating a process of conductive film formation is increased. In addition, the width (W) of the conductive strip also can be varied, and the reliability of the evaluation is increased by manufacturing a plurality of test patterns of different lengths or widths.
The method for evaluating a process of conductive film formation using test patterns of
FIGS. 1 and 2
is as follows. First of all, the sheet resistance Rsh is obtained from the cross resistor pattern shown in
FIG. 1
using the van der Pauw equation.
In addition, the resistance Rdb of the conductive strip
210
is obtained by applying a current through the conductive strip
210
. Then, the actual length and width (Weff, Leff) of the pattern of
FIG. 2
implemented on the semicondcutor substrate is measured.
Next, the sheet count (sc) i.e., the value obtained by dividing the length Leff by width Weff of the conductive strip is calculated, and then the whole resistance Rdb is divided by the sheet count (sc), thereby obtaining the sheet resistance Rsh′ in a strip-type pattern such as FIG.
2
.
Then, in a case where the sheet resistances Rsh and Rsh′ are identical or similar to one another in comparison, it is assumed that the process is properly performed. In a case the process was properly performed on a wafer, subsequent processes for fabricating semiconductor devices follow on the wafer. However, in a case where the difference between the sheet resistances Rsh and Rsh′ deviates from an allowable value, the reilaibility of the device is reduced. Thus, the wafer is disposed of without performing subsquent processes.
However, the conventional method for evaluating a process of silicide film formation using test patterns has the following problems.
In a case where the width of a silicide pattern desired to be tested is the critical dimension or less, the difference between the dimension of the pattern on the photo mask and the dimension of the test pattern actually implemented on the semiconductor substrate is large due to exposure effect in a photolithography process. Consequently, the dimension of a manufactured test pattern needs to be measured, whereby it takes a long time to perform a test, and the test is made complicated.
In addition, on a conductive pattern having a smaller width than the critical dimension, a silicide film is not formed properly. Even if it is formed, when its phase is transited to a low resistance silicide by annealing, the phase transition is not properly made. Thus, the resistance is much higher than that of a silicide of a larger width, the thermal stability is low, and the uniformity is reduced. Therefore, in case of a silicide pattern having a smaller width than the critical dimension, the correlation between the line width and the resistance is irregular, and, accordingly it is difficult to evaluate the process of silicide film formation by an electric measuring method. Due to this, the line width of the pattern is measured by handwork, so it takes a long time to evaluate the process, and the reliability of the evaluation is reduced.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a test pattern for evaluating a process of silicide film formation in which the evaluation time is shortened, and the reliability of the evaluation is increased, by rapidly measuring the thickness of a silicide film having a line width smaller than the critical dimension by an electric method.
To achieve the above objects, there is provided a test pattern in accordance with the present invention which includes: a silicon substrate having an active region and a field region; a first pattern composed of a cross resistor pattern of a polycide layer formed on the field region; and a second pattern composed of polycide layer and a silicide layer formed on the active region. The first pattern includes: two polycide layer patterns having the same width formed to be orthogonal to each other; a first current contact pad and a first voltage c
Fleshner & Kim LLP
Hyundai Electronics Industries Co,. Ltd.
Loke Steven
LandOfFree
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