Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2002-07-18
2004-06-22
Nguyen, Van Thu (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S189040, C365S191000
Reexamination Certificate
active
06754116
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for testing a semiconductor memory having a plurality of memory banks, in which commands are generated and testing is effected to determine whether or not the commands are executed by the memory banks, single-bank commands for testing a respective single memory bank being generated and assigned to selected memory banks. The invention furthermore relates to a method for testing a semiconductor memory having the plurality of memory banks, single-bank commands for accessing a respective single memory bank being generated and executed for test purposes, and testing being effected to determine whether or not the commands are executed correctly by the memory banks.
The invention furthermore relates to a semiconductor circuit having a semiconductor memory including a plurality of memory banks. The semiconductor circuit has a built-in self-test (BIST) processor that generates single-bank commands for testing individual memory banks. The invention additionally relates to a semiconductor circuit having a semiconductor memory including memory banks and such a BIST processor.
Integrated semiconductor circuits with semiconductor memories often have an integrated switching unit that, upon start-up of the semiconductor circuit, automatically carries out a functional test of the integrated semiconductor memory. Such a switching unit is provided on many microprocessors and is designated according to its function as BIST because a microprocessor into which this switching unit is integrated automatically carries out a self-test of its own semiconductor memory when it is activated, i.e., supplied with current.
Furthermore, there are test devices with which memories of semiconductor circuits can be tested in a targeted manner. These test devices are very complicated and unwieldy and serve for carrying out more complex and more diverse functional tests on semiconductor memories in individual experiments.
Semiconductor circuits occasionally have a selection unit, a so-called multiplexer, with which either self-test signals generated on the test controller or external commands conducted into the test controller externally can be selected to carry out the memory test.
The switching unit for generating the self-test commands (BIST) and, if appropriate, the multiplexer are part of a test controller that is integrated as switching region into a semiconductor circuit such as, for instance, an application specific integrated circuit (ASIC). Commands output by the test controller are forwarded to the semiconductor memory, for example, to an embedded DRAM, and the execution of the commands by the DRAM is monitored and evaluated by the test controller. The test result lies in an indication of whether or not memory areas function as intended and, if appropriate, which memory areas do not function as intended.
Semiconductor memories usually include a plurality of memory areas that can be addressed independently of one another, the memory banks. The size of an integrated semiconductor memory depends on the number of memory banks present and on the number of memory cells per memory bank, expressed in the number of row addresses and column addresses. The number and memory size of the memory banks are determined by the application for which the semiconductor memory is used.
If a semiconductor memory is tested for its functionality, then the operations that each memory cell must be able to perform during the operation of the memory are carried out on a sample basis, commands being successively conducted to all the memory cells of the semiconductor memory and the correct execution of these commands being tested. In such a case, the commands “read” and “write” for the reading and writing of information items are tested, and also commands “activate” and “precharge” for activating and deactivating a memory cell for a write or read operation. Such a command constitutes a single-bank command because, at one point in time, it can only ever be used to test a single memory bank.
A plurality of single-bank commands are carried out successively by all the memory cells of a memory bank and successively in all the memory banks. As such, it is possible to test the basic functions of a memory cell in the entire memory.
During operation of the semiconductor circuit, however, the semiconductor operations to be formed are more complex. At a specific clock cycle time, it is usually not just a single memory cell that is addressed, but rather a plurality of memory cells and, in particular, those of different memory banks. By way of example, while an information item is stored in a memory cell of a first memory bank or is read from it, at the same time a memory cell of a second memory bank is prepared for the writing or reading of information items. Therefore, a plurality of memory banks is usually accessed at every clock cycle time.
Such an access has not been able to be carried out by testing heretofore. Above all, the switching units (BIST) developed for the automatic self-test are only able to generate commands for a memory cell of a single memory bank and to forward them to the relevant memory bank. These single-bank commands are not suitable, however, for testing more complex memory interrogations than the basic functions of an individual memory cell.
It would be desirable to be able also to simulate more complex accesses to a plurality of memory banks simultaneously for test purposes when a memory is activated. Such a process would necessitate new development of a test controller, for example, the BIST unit thereof for generating the command sequences so that commands that simultaneously address a plurality of memory banks are also generated.
Such a new development can only be achieved with a high outlay in respect of time and costs. So that the costs for the development of new integrated semiconductor circuits are kept low, a new development of the test controller, in particular, its BIST processor, is usually left out of consideration. As a result, the self-test as is performed on conventional BIST circuits remains limited to the single-bank commands.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a test of a semiconductor memory having a plurality of memory banks that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that enables a test in which memory cells of different memory banks of a semiconductor memory are addressed simultaneously by testing, and, at the same time, the costs and the outlay for such a test are kept low.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a method for testing a semiconductor memory having a plurality of memory banks, including the steps of generating respective single-bank commands for testing a single one of the memory banks and assigning the commands to selected ones of the memory banks, combining a plurality of single-bank commands to form a multibank command, the single bank commands of the multibank command being executed simultaneously by the memory banks to which the single bank commands are respectively assigned, and effecting a test to determine if the selected ones of the memory banks jointly execute the multibank command.
According to the invention, a plurality of single-bank commands are combined to form a multibank command, as constituents of which they can be executed simultaneously by the various memory banks to which they are respectively assigned, and, in that, testing is effected to determine whether or not the selected memory banks jointly execute the multibank command.
According to the invention, multibank commands are formed that are required for test access to a plurality of memory banks simultaneously. However, these multibank commands are not generated directly, which would necessitate a complete new development of a test controller and of the method, i.e., its mode of operation. Instead, multibank commands are generated in two steps,
Janik Thomas
Kuhne Sebastian
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Nguyen Van Thu
Stemer Werner H.
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