Test mode method and apparatus for internal memory timing...

Details Test mode method and apparatus for internal memory timing... Test mode method and apparatus for internal memory timing...

2008-03-04

2008-03-04

Dinh, Son (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S201000

Reexamination Certificate

active

11227099

ABSTRACT:
A method of testing internal signals of a memory for timing marginalities which may result in unstable operation includes: delaying internal address signals of the memory by an amount great enough so that data cannot be validly written to and read from memory locations which are accessed by address signals having timing marginalities which are delayed but small enough so that data can be validly written to and read from memory locations which are accessed by address signals not having such timing marginalities which are delayed. Data is then written to and read from memory locations which are accessed by delayed address signals, and a determination is made as to whether the data read from any memory location does not correspond with the data written to such memory location.

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