Test mode matrix circuit for an embedded microprocessor core

Details Test mode matrix circuit for an embedded microprocessor core Test mode matrix circuit for an embedded microprocessor core

1997-09-11

1999-09-21

Le, Dieu-Minh T.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714724, 307407, G06F 1100

Patent

active

059548240

ABSTRACT:
A test mode matrix circuit in an integrated circuit switches signal lines internal to the integrated circuit in a manner that allows an embedded microprocessor within the integrated circuit to be fully functionally tested using standard test vectors applied to the integrated circuit, and which allows for debugging the code written for an embedded microprocessor core by connecting an in-circuit emulator (ICE) to the integrated circuit. The test mode matrix circuit operates in a number of mutually exclusive modes, each of which is suitably selected via control signal inputs to the test mode matrix. The test mode matrix circuit couples signals from the embedded microprocessor to the application-specific logic without passing through off-chip drivers/receivers. Multiple microprocessors and corresponding test mode matrices may also be implemented on the same integrated circuit.

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