Test mode for verification of on-chip generated row addresses

Details Test mode for verification of on-chip generated row addresses Test mode for verification of on-chip generated row addresses

2000-12-26

2001-12-11

Fears, Terrell W. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S201000

Reexamination Certificate

active

06330203

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention generally relates to a semiconductor memory and more particularly, to a circuit and method to verify the generation of row addresses during auto-refresh or self-refresh of a dynamic random access memory (DRAM), fabricated on an integrated circuit (IC).
(2) Description of Prior Art
In a standard dynamic random access memory (DRAM), memory cells are arranged in an array. Each cell is connected to one of a plurality of word lines and to one of a plurality of bit lines. Memory addressing is provided by placing the proper voltage levels on the word and bit lines.
Each memory cell in the array of a typical DRAM is comprised of one metaloxide-semiconductor field-effect transistor (MOSFET) and a single capacitor. Binary data is stored to the memory cell by setting the level of charge on the capacitor. However, charge leakage on the capacitor requires that the capacitor be periodically refreshed (recharged) in order to maintain the original data charge level.
In typical DRAMs, this periodic refresh operation is controlled by internal circuitry, and is referred to as an auto-refresh or self-refresh operation. Self-refresh is initiated internally and generates refreshes based upon internal timing, while auto-refresh is initiated externally providing one refresh per external command. During this refresh, the write path to the memory array is locked out, and internally generated signals address the memory locations and rewrite the data to the memory cells. To test that the addresses are generated correctly, a test mode that allows the device to write data during the auto-refresh is generally used. This is achieved using minimal additional logic along with the external row address strobe (RAS), column address strobe (CAS), write enable (WE) and data signals. Refer now to
FIG. 1
showing a flow diagram of testing of proper addressing of the word lines on one bit line. Initially, data are written to each of the plurality of memory locations with corresponding word lines on one of the bit lines (
10
). The refresh test mode is then initiated (
12
). An auto-refresh command results in the writing of inverted data to the wordline currently being accessed by the refresh operation (
14
). Validation of addressing is accomplished by observing that the originally stored data is inverted (
16
).
A typical timing diagram for auto-refresh entry for fast page (FP) and extended data output (EDO) RAM devices is shown in
FIG. 2
a
, and for a synchronous DRAM (SDRAM) device in
FIG. 2
b
. The auto-refresh is initiated by first bringing an active low write enable (!WE) to a high level This is followed by sequentially bringing the active low column address strobe (!CAS) and row address strobe (!RAS) to low (
0
). In FP and EDO RAM devices (
FIG. 2
a
), this condition will initiate the auto-refresh cycle. In SDRAM devices (
FIG. 2
b
), the clock (CLK) edge is used to synchronously start the auto-refresh when !WE, !CAS and !RAS are
1
,
0
and
0
, respectively.
A timing diagram for auto-refresh with a write after test mode entry (depicted in
FIG. 1
) for an FP or EDO device is shown in
FIG. 3
a
Auto-refresh entry is accomplished as described earlier (in
FIG. 2
a
). Inverted data is written to the memory cell when the three active low signals !RAS, !CAS and !WE are all low.
FIG. 3
b
shows a timing diagram for an auto-refresh with a write after test mode entry for a SDRAM. Auto-refresh entry is accomplished as depicted in
FIG. 2
b
. Inverted data is synchronously written to the memory cell on the rising clock (CLK) edge when the three active low signals !RAS, !CAS and !WE are high (
1
), low (
0
) and low (
0
), respectively.
Since the self-refresh operation and auto-refresh operation use the same core control signals, (RAS, CAS and WE) the address generation testing for auto-refresh may be applied to the test mode used for self-refresh However, in packet based memory protocols (such as Direct Rambus DRAM or DRDRAM), the interface logic between the IC input/output (I/O) and memory array generate the refresh addresses and the core control signals (functioning similarly to RAS, CAS, WE, etc.). Since the core control signals may not be directly manipulated concurrently with a refresh operation, a write event cannot be initiated as easily as in a standard DRAM. Because of this, additional interface logic may be required to manipulate the core signals.
Other approaches for detecting refresh address signals in memory devices exist. U.S. Pat. No. 5,299,168 to Kang describes a circuit that stores the initial values of the refresh address counter (all 0s) and bit-wise compares them individually using an exclusive OR (XOR) to the final values of the refresh address counter (all 1s). The outputs of the plurality of XORs are ANDed; a high output at the end of the refresh cycle indicates that both logic states are possible on each of the bits of the refresh address counter. It fails to determine, however, if two of the refresh address counter bit lines are shorted together. U.S. Pat. No. 5,446,695 and 5,703,823 to Douse et al. teach a method with a self-refreshing circuit that permits programming and verification of the self-refresh time. U.S. Pat. No. 5,959,929 to Cowles et al. teaches a method for writing to multiple banks of a memory device. It permits different rows in the banks to be activated simultaneously.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide a circuit that facilitates verification of proper address generation in packet based memory protocol (Direct RDRAM) devices during the auto-refresh or self-refresh cycle.
A second object of the present invention is to provide a method for verification of proper address generation in packet based memory protocol (Direct RDRAM) devices during the auto-refresh or self-refresh cycle.
A further object of the present invention is to provide a circuit facilitating verification of proper address generation in packet based memory protocol (Direct RDRAM) devices during the auto-refresh or self refresh cycle that does not require changes to the interface logic or core signal generation.
A still further object of the present invention is to provide a circuit and method facilitating verification of proper address generation in DRAM devices during the auto-refresh or self-refresh cycle that does not require changes to the interface logic or core signal generation.
These objects are achieved using a method of verifying the generation of row addresses in a semiconductor memory comprising setting the logic level on all of a plurality of memory cells on one bit line of a semiconductor memory to a set level (all low or all high). Control signals are used to initialize a test mode and then to initiate a refresh cycle thereby sequentially addressing each word line of the memory cells and changing the logic level on the memory cells to the opposite level. Standard memory addressing is used to observe that the logic level on each of the memory cells has changed after exiting the test mode, thereby verifying proper generation of the row addresses. A memory cell that has not changed state after the test mode refresh cycle indicates a row addressing error.
Also, in accordance with the objects of this invention, a method of using a standard sense amplifier circuit facilitating proper verification of row address generation is achieved. This requires minimal additional logic while using the core control signals functioning similarly to the RAS, CAS, and WE signals in a standard DRAM. The difference between the prior art method of stimulating the sense amplifier circuit and the method of the present invention is the manipulation of the control signals during the test mode. The sense amplifier has two bit lines connected to a plurality of memory cell pass gates and memory cells each of which is addressed by a different word line. A shorting pass gate activated by signal EQ will connect the two bit lines together while two volta

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