Test mode entrance through clocked addresses

Details Test mode entrance through clocked addresses Test mode entrance through clocked addresses

1998-04-03

1999-12-21

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Testing

365233, G11C 700

Patent

active

060058145

ABSTRACT:
A robust system for entering a test mode in an integrated circuit, for example, a memory device, greatly eliminates the probability of unintentionally entering the test mode, yet provides a system of access through a precise address and control pin sequence. By using an existing control pin present on the integrated circuit as a clock signal input for a series of latches, the present scheme sets up a number of address with predetermined values in order to create a key that is correct only if all the addresses are at the correct values. The key, combined with the clock signal input, allows a test mode enable signal to pass through each latch in a series. By further requiring that the address sequence for the key be input during an otherwise "illegal" operation for the integrated circuit, the present scheme further ensures that unintentional entry to the test mode is avoided.

REFERENCES:
patent: 5781485 (1998-07-01), Lee et al.

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