Test mode controller

Details Test mode controller Test mode controller

2008-05-13

2008-05-13

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Read/write circuit

Testing

C365S191000

Reexamination Certificate

active

11529274

ABSTRACT:
A test mode controller is capable of reducing a chip area and unnecessary current consumption by integrally constructing latch units of the two test circuits. The test mode controller includes a test control block for determining a test mode between a programmable test and a wafer burn-in test to generate a reset signal and a control signal generating block for receiving a plurality of input signals activated in a wafer burn-in test to generate a plurality of test control signals in response to the reset signal and a programmable test signal activated in a programmable stress test.

REFERENCES:
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patent: 6949947 (2005-09-01), Jung
patent: 2005/0138502 (2005-06-01), Jung
patent: 2005/0207245 (2005-09-01), Kang
patent: 2007/0018677 (2007-01-01), Marr
patent: 2007/0076495 (2007-04-01), Mochida et al.
patent: 2007/0162799 (2007-07-01), Kamada
patent: 2001-210099 (2001-08-01), None
patent: 10-2000-0055257 (2000-09-01), None
patent: 10-2003-0051030 (2003-06-01), None

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