Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
1999-12-09
2001-10-02
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S189090
Reexamination Certificate
active
06297996
ABSTRACT:
BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to the field of semiconductor memories, and is more specifically directed to special test modes for exercising such memories, and more specifically to the operation of burn-in test modes for such memories.
Integrated circuits typically operate for long periods of time without failure. However, a significant number of integrated circuits fail within the first days of operation. This infant failure of circuits is unacceptable to equipment manufacturers who incorporate the circuit into their equipment. Therefore, circuit manufacturers must find those circuits subject to infant failure.
Circuits subject to infant failure usually test good in the initial tests prior to operation, but will fail a short time after they are used. One method of detecting circuits subject to infant failure is to test them under extreme conditions to accelerate the aging of the circuit. Circuits subject to infant failure will fail under these conditions. The circuits that do not fail will typically operate for a long period of time.
One way to test circuits under extreme conditions is to place them in a burn-in oven to elevate the temperature of the circuit. The components of the circuit are then exercised by applying voltages significantly above the normal operating voltage of the circuit. This is typically done after the circuit is packaged, and the over-voltages are applied to the pins of the device, although the circuit can be placed in a burn-in oven before it is packaged and the over-voltages applied to the pads by connecting the pads to the probes of test equipment. When the circuit is packaged after testing the entire device is placed into a bread board with many other devices and all are tested at the same time. The time savings in testing all of the devices at the same time compared to the time that would be required in testing the unpackaged circuits individually on testers or connecting all the unpackaged circuits to a testing tape and testing them simultaneously outweighs the cost of packaging the circuits that fail during the burn-in test.
The burn-in test can require many hours, typically anywhere from one to ninety-six hours. The burn-in cycle is typically long, it can be up to several microseconds. As observed by the current inventor, the cycle time of a circuit can be much shorter than that. It can be as low as 5 ns. Thus, after 5 ns the component being exercised is inactive, due to the circuit internally timing out, wasting 99.5% of the burn-in cycle.
The test modes, including the burn-in test mode where the device is exercised in a burn-in oven, can be entered in several ways. One way of entering the test mode is to set aside a pin for entering the test mode. However, most devices are pin limited. All the pins on the device are already used for some functionality and to set one of them aside for testing would require giving up some functionality, making the device less competitive. Another problem with setting aside a pin for testing is that it changes the pinout of the device from the standard pinout and makes it not compatible with similar devices by other manufacturers where that pin is used for some functionality.
Another way to enter the test mode is clocking and latching the required test mode conditions into the circuit. This does not tie up a pin either on a permanent basis or even while the device is in the test mode. Unfortunately though this allows the test mode to be entered accidentally if the test conditions are clocked and latched into the device during regular use of the circuit or during power up. Accidentally entering the test mode can significantly alter the data stored in the device when the device is a memory circuit. Additionally, since the test conditions are now latched into the device it is very difficult to exit the test mode. Furthermore, this test may be difficult to enter into in the burn-in oven because typically burn-in ovens have limited capabilities in controlling and clocking the signals.
The test mode can also be entered by supplying a voltage higher than the operating voltage of the device (an over-voltage) to one or more pins for the duration of the test mode. This poses the problem of entering the test mode accidentally due to overshoots on the selected pin due to noise. This again poses the problem of possible loss of data stored in the device due to the replacement of the user's data. Additionally, because the burn-in oven may have limited control of signals, not all burnin ovens are capable of over-voltages, so this method of entering the bumn-in test mode is only available for some bumn-in ovens.
Further background on memories can be found in: Prince, Betty, SEMICONDUCTOR MEMORIES, A HANDBOOK OF DESIGN, MANUFACTURE, AND APPLICATION, 2nd ed., John Wiley & Sons, 1991; ISSCC proceedings from 1975 to the present, all incorporated herein by reference.
SUMMARY THE INVENTION
The present application discloses methods and circuits for a memory device to enter a test mode by setting a first power supply terminal to the opposite logic state it is set to in the normal operation mode. Once the memory device enters the test mode the circuitry that resets the memory device after a read or write mode is disabled and the reset is controlled by a test mode cycle control node. This allows the wordlines and bitlines of the memory device to be stressed for a longer period during the test mode by reducing the frequency at which a reset is generated. In a preferred embodiment of the invention the test mode cycle control node is connected to an internal or external clock and the cycle of the clock is lengthened.
In the preferred embodiment of the invention the first power supply terminal is the power supply terminal of the input/output pins. In this embodiment a test mode write data pin instead of the input/output pins is used to generate a data state to write to the memory cell.
Once the test mode is entered it should test every component of the circuit. When the circuit is a memory device it is the goal to exercise the wordlines in both a high and a low state for some significant period of time, it being particularly important to exercise the wordlines in a high data state. The burn-in cycle is long; it can range from hundreds of nanoseconds up to a full microsecond. Unfortunately, the circuit cycles at a much faster speed. For some of the faster memory circuits the cycle time can be as low as 5 nanoseconds.
A significant advantage of this invention is that the wordlines and bitlines can be made active for a much larger duration of the burn-in cycle. As recognized by the current inventor, in the prior art the wordlines and bitlines of a memory device only remain active for the circuit's effective time active per cycle of the normal operational mode. The circuit then internally times out and the wordlines and bitlines become inactive, and therefore not under stress, for the remainder of the burnin cycle, not utilizing over 90% of the burn-in cycle. In order to stress the wordlines and bitlines for the full duration of a burn-in cycle the circuit will have to stay in the burn-in oven for as many burn-in cycles as needed for the circuit's effective time active per cycle to add up to the effective time active per burn-in cycle, each time wasting over 90% of the burn-in cycle time. For example, if the burn-in cycle is 1000 ns, and the circuits cycle is 5 ns, the given wordline and associated bitlines remain active for only 0.5% of the burn-in cycle. To stress a wordline and bitline for the full 1000 ns of a burn-in cycle would require that they remain in the burn-in oven for 200 burn-in cycles, a total of 200 &mgr;s (200,000 ns), only 1000 ns of which is used, and the remaining 199 &mgr;s wasted. The memory device must be kept in the burn-in oven 200 times longer than if the wordline was active for the entire burn-in cycle. It is usually desired to stress each wordline for about 1 second, so the above process is repeated several thousand times for each wordline.
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Galanthay Theodore E.
Jorgenson Lisa K.
Le Vu A.
STMicroelectronics Inc.
Thoma Peter J.
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