Test mode activation and data override

Details Test mode activation and data override Test mode activation and data override

1996-01-19

2000-11-07

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Testing

36518909, 365226, G11C 700

Patent

active

061445940

ABSTRACT:
A memory device with a test mode control circuit for entering a test mode responsive to a high on the Vss pin or a low on the Vcc pin that supply power to the output pins during normal operation of the memory device. In test mode the wordlines and bitlines of the memory remain active from the time they are activated, typically when the clock switched from a first to a second logic state, until the clock switches back to the first logic state.

REFERENCES:
patent: 5072137 (1991-12-01), Slemmer
patent: 5072138 (1991-12-01), Slemmer et al.
patent: 5115146 (1992-05-01), McClure
patent: 5134586 (1992-07-01), Steele
patent: 5134587 (1992-07-01), Steele
patent: 5161159 (1992-11-01), McClure et al.
patent: 5299203 (1994-03-01), Steele
patent: 5408435 (1995-04-01), McClure et al.
patent: 5424988 (1995-06-01), McClure et al.
patent: 5440178 (1995-08-01), McClure
patent: 5463585 (1995-10-01), Sanada
patent: 5463595 (1995-10-01), Sanada

Affiliated with

Also associated with

Rating

Test mode activation and data override does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Test mode activation and data override, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test mode activation and data override will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1648046