Test mode accessing of an internal cache memory

Details Test mode accessing of an internal cache memory Test mode accessing of an internal cache memory

1997-03-14

2002-09-03

Bragdon, Reginald G. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S123000, C711S125000, C711S126000, C714S030000

Reexamination Certificate

active

06446164

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to integrated circuits, and in particular, relates to the design of microprocessors.
DESCRIPTION OF RELATED ART
Exploiting the property of locality of memory references, cache memories have been successfully used to achieve high performance in many computer systems. In the past, cache memories of microprocessor-based systems are provided off-chip using high performance memory components. This is primarily because the amount of silicon area necessary to provide an on-chip cache memory of reasonable performance would have been impractical, since increasing the size of an integrated circuit to accommodate a cache memory will adversely impact the yield of the integrated circuit in a given manufacturing process. However, with the density achieved recently in integrated circuit technology, it is now possible to provide on-chip cache memory economically.
In a computer system in which a cache memory is provided, when a memory word is needed, the central processing unit (CPU) looks into the cache memory system for a copy of the memory word. If the memory word is found in the cache memory, a cache “hit” is said to have occurred, and the main memory is not accessed. Thus, a figure of merit which can be used to measure the effectiveness of the cache memory is the “hit” ratio. The hit ratio is the percentage of total memory references in which the desired datum is found in the cache memory without accessing the main memory. When the desired datum is not found in the cache memory, a “cache miss” is said to have occurred. In addition, in many computer systems, there is one or more portions of the address space which is not mapped to the cache memory. This portion of the address space is said to be “uncached” or “uncacheable”. For example, the addresses assigned to input/output (I/O) devices are almost always uncached. Both a cache miss or an uncacheable memory reference results in an access to the main memory.
In the course of developing or debugging a computer system, it is often necessary to monitor program execution by the CPU or to interrupt one instruction stream to direct the CPU to execute certain alternate instructions. For example, a technique for testing a microprocessor in a system under development uses an in-circuit emulator (ICE) which provides facilities to monitor and intervene in the CPU's instruction stream. The ICE typically monitors the signals on the microprocessor's pins. In one mode of ICE operation, when a predetermined condition in the program execution is encountered, the ICE causes alternative instructions to be executed for such purpose as reading or altering the internal states of the CPU. Such alternative instructions can be preloaded into the cache memory or excluded from the cache memory. The ability to load or exclude such instructions into or instructions from the cache memory from a source external to the CPU can be very useful in many applications. Such ability is not known in the prior art.
When the cache memory is implemented off-chip, the ICE can easily isolate the cache memory and perform diagnostic test on each cell in the cache memory by using such techniques as exhaustive standard memory test algorithms independent from the operation of the CPU. In addition, the transactions between the cache memory and the CPU can be monitored by the ICE on the off-chip bus between the cache memory and the CPU. Hence, no difficulty is created in testing or using an off-chip cache. However, when the cache memory is implemented on-chip, the transactions between the cache and the CPU occur on an on-chip bus, which cannot be probed from the pins of the integrated circuit. As a result, debugging operations using an ICE in a system with an on-chip cache system can be very restricted. The inability to access and exhaustively test the internal cache makes diagnosing certain system problems difficult. When the on-chip cache achieves a high hit ratio, only the relatively infrequent accesses to main memory due to cache misses or references to uncacheable parts of memory can be monitored from the pins.
SUMMARY OF THE INVENTION
In accordance with the present invention, a structure and a method provide read and write accesses to a microprocessor's internal cache. During write access, an external data bus transmits to an internal data bus an address, cache tags and data in accordance with a clock signal provided externally. During read access, the external data bus transmits an address and receives from the internal data bus data and tag, also in accordance with the clock, signal provided externally.
In one embodiment, during write access, the external data bus is time-multiplexed to transmit the address, the cache tags and data in two clock periods of an externally provided clock signal. In the same embodiment, during read access, the external data bus is time-multiplexed to transmit to the internal data bus an address in the first clock period of the external clock signal, and to receive cache tags and data in the next two successive clock periods of the externally provided clock signal. In this embodiment, “reserved” pins are used to specify a cache access mode. Control signals for the cache access are provided via pins which are used during functional operation to receive external interrupt signals.
The present invention allows the user of the microprocessor to exhaustively test the on-chip cache using standard memory test algorithms. The present invention also allows preloading the on-chip cache under control of signals external to the microprocessor. Such preloading operations can be useful in certain applications. In addition, the present invention provides a facility for external testing equipment to monitor or intervene internal operations of the microprocessor.


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