Test method of one chip micro-computer and one chip micro-comput

Details Test method of one chip micro-computer and one chip micro-comput Test method of one chip micro-computer and one chip micro-comput

1998-01-29

2000-06-27

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C06F 1100

Patent

active

060819081

ABSTRACT:
When testing internal state of one chip micro-computer having a CPU and a ROM installed in a single package, data D read from the ROM is subjected to non-degenerate conversion using data DT from the outside and is executed as a command code by the CPU in a test mode. To input the data DT which can serve as a correct command code from the outside, it is necessary that the data D is known. A third party is incapable of conducting a test for testing the internal state and wrongfully reading the written data.

REFERENCES:
patent: 5228139 (1993-07-01), Miwa et al.
patent: 5671275 (1997-09-01), Ezuriko
patent: 5704033 (1997-12-01), Park
patent: 5784589 (1998-07-01), Bluhm
patent: 6003141 (1999-12-01), Ishida

Affiliated with

Also associated with

Rating

Test method of one chip micro-computer and one chip micro-comput does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Test method of one chip micro-computer and one chip micro-comput, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test method of one chip micro-computer and one chip micro-comput will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1793614