Test method for ferroelectric memory

Details Test method for ferroelectric memory Test method for ferroelectric memory

2007-07-03

2009-02-03

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Testing

C365S145000

Reexamination Certificate

active

07486578

ABSTRACT:
A ferroelectric memory includes a cell block that includes: a block select transistor arranged between a bit line and a local bit line; memory cells arranged between the local bit line and a plate line, each of the memory cells contains a cell transistor and a ferroelectric capacitor connected in series; and a reset transistor arranged between the local bit line and the plate line. A test method for the ferroelectric memory includes: applying a potential that allows the cell transistors to be ON to the word lines; applying a potential that allows the reset transistor to be OFF to the reset line; applying a potential that allows the block select transistor to be ON to the block select line; and applying a stress voltage between the bit line and the plate line.

REFERENCES:
patent: 6094370 (2000-07-01), Takashima
patent: 6151242 (2000-11-01), Takashima
patent: 6618284 (2003-09-01), Shimada et al.
patent: 2002-313100 (2002-10-01), None
patent: 2005-209324 (2005-08-01), None

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