Test method for a semiconductor memory

Details Test method for a semiconductor memory Test method for a semiconductor memory

2006-10-10

2006-10-10

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S230030, C365S200000

Reexamination Certificate

active

07120071

ABSTRACT:
A testing method for a semiconductor memory includes the steps of storing data in each of a plurality of memory cell blocks, electrically connecting two memory cell blocks with a sense amplifier shared by the two memory cell blocks of the plurality of memory cell blocks, sensing data of the two memory cells through the sense amplifier and determining whether the sensed data is normal based on a bit line capacitance increase according to the connection of the two memory cell blocks. The testing method can intentionally reduce an offset margin of a memory cell through increase of bit line capacitance, remove and screen an abnormal memory cell having a smaller capacitance and effectively decrease testing time.

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patent: 6167541 (2000-12-01), Siek et al.
patent: 6480433 (2002-11-01), Huffman

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