Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent
1997-08-22
1999-12-14
Chung, Phung M.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
714733, G11C 2900
Patent
active
060031492
ABSTRACT:
A method of testing a memory array is disclosed, the method comprising writing a test pattern to the memory array in as few as one or two RAS cycles by first activating the input/output data lines and then selectively activating multiple rows and columns. The method can be used with a variety of test environments. For example, the disclosed method may be implemented in testing using automated test equipment, and may also be incorporated in devices having built-in self-test circuitry. The disclosed method reduces the time required to test the memory array with minimal additional circuitry and no encroachment on valuable die real estate.
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Han, S.H., et al., "Two-Dimensional Multiple-Access Testing Technique for Random-Access Memories", IEEE, 248-251, (1986).
Kraus, R., et al., "Design for Test of MBIT DRAMs", IEEE Int'l Test Conference, 316-321, (1989).
Beffa Ray
Cloud Eugene H.
Farnworth Warren M.
Nevill Leland R.
Waller Ken
Chung Phung M.
Micro)n Technology, Inc.
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