Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1999-06-29
2004-03-30
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S201000
Reexamination Certificate
active
06715114
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and apparatus for testing semiconductor devices such as semiconductor memory devices, and semiconductor devices produced by such a testing method or apparatus.
2. Description of the Related Art
Recent semiconductor memory devices have an increased memory capacity, which increases the time and cost necessary for testing the semiconductor memory devices.
The fraction of faulty chips can be obtained by a monitor test performed during the burn-in process after packaging and/or a final test after the burn-in process. If the fault rate of each lot calculated based on the fraction of faulty chips does not reach a given reference value, the burn-in process, which considerably increases the cost of testing, will further be performed.
In such a case, the additional burn-in increases the cost of testing the semiconductor devices. It may be required to additionally or newly invest in the facility for testing the semiconductor devices. Thus, the final cost of semiconductor devices is increased in order to withdraw the additional cost and the investment.
Conventionally, only faulty bits on a wafer are found under the normal operating condition during the test performed before packaging and are replaced by redundant bits. The burn-in is carried out at the stage of the final test performed after packaging and it is only determined whether each packaged chip is faulty. The faulty packaged chips are thus discarded.
SUMMARY OF THE INVENTION
It is an object of the present invention to efficiently and effectively test the semiconductor devices and to thus reduce the production cost.
The above object of the present invention is achieved by a semiconductor device testing apparatus comprising: a first part which repeatedly performs a wafer-level burn-in to chips formed on a wafer; and a second part which detects a progress of occurrence of faulty cells in each of the chips.
The above object of the present invention is also achieved by a method of testing a semiconductor device comprising the steps of: (a) repeatedly performing a wafer-level burn-in to chips formed on a wafer; and (b) detecting a progress of occurrence of faulty cells in each of the chips.
The above object of the present invention is also achieved by a semiconductor device comprising: a chip which is one of chips formed on a wafer and subjected to a wafer-level burn-in by a predetermined number of times; and a redundant circuit which replaces the faulty cells with redundant cells in accordance with a progress of occurrence of the faulty cells.
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De'cady Albert
Fujitsu Limited
Torres Joseph D.
Westerman Hattori Daniels & Adrian LLP
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