Test masks for lithographic and etch processes

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C700S121000, C702S097000

Reexamination Certificate

active

10321281

ABSTRACT:
A mask design is generated for patterning a test wafer using a lithographic or etch process, the process is characterized based on the patterned test wafer, and a pattern-dependent model is used based on the characterization to predict characteristics of integrated circuits that are to be fabricated by the lithographic or etch process.

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